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US 2026/0252489 A1Published application
Elastic configuration of data rate control parameters in a memory sub-system with single-level cell memory caching
AssigneeMicron Technology, Inc.
InventorsPaul Roger Stonelake, Byron D. Harris, Ramkumar Venkatachalam
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Abstract
Processing logic in a memory sub-system monitors an amount of free space in a cache of a memory device, determines an operating gear of a host system based on the amount of free space in the cache of the memory device, and configures one or more data rate control parameters of the system based on the operating gear of the host system.
Claims21
-20. (canceled)
A system comprising:
- a memory device comprising a cache and a primary storage band;
- and
- a processing device, operatively coupled with the memory device, to perform operations comprising:
- monitoring an amount of free space in at least one of the cache or the primary storage band;
- and
- configuring a target rate for migrating data from the cache to the primary storage band based on the amount of free space.
3 more elements
A method comprising:
- monitoring, by a processing device, an amount of free space in at least one of a cache of a memory device or a primary storage band of the memory device;
- and
- configuring, by the processing device, a target rate for migrating data from the cache to the primary storage band based on the amount of free space.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- monitoring an amount of free space in at least one of a cache of a memory device or a primary storage band of the memory device;
- and
- configuring a target rate for migrating data from the cache to the primary storage band based on the amount of free space.
Dependencies are inferred from the claim text.