G06F 13/4059
Where the synchronisation uses buffers
Official title: {where the synchronisation uses buffers, e.g. for speed matching between buses}
G06F13/4059 (Where the synchronisation uses buffers) appears on 601 US grants and 479 published applications in this corpus.
Search patents in G06F- Granted patents
- 601
- Published applications
- 479
- Assignees
- 242
- Inventors
- 1,243
- Latest grant
- 18 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1982 | 1 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 2 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 2 | 0 |
| 1992 | 3 | 0 |
| 1993 | 2 | 0 |
| 1994 | 4 | 0 |
| 1995 | 4 | 0 |
| 1996 | 4 | 0 |
| 1997 | 11 | 0 |
| 1998 | 14 | 0 |
| 1999 | 19 | 0 |
| 2000 | 26 | 0 |
| 2001 | 17 | 0 |
| 2002 | 29 | 21 |
| 2003 | 34 | 37 |
| 2004 | 34 | 29 |
| 2005 | 20 | 13 |
| 2006 | 20 | 32 |
| 2007 | 23 | 24 |
| 2008 | 25 | 33 |
| 2009 | 14 | 27 |
| 2010 | 23 | 19 |
| 2011 | 26 | 18 |
| 2012 | 23 | 21 |
| 2013 | 23 | 17 |
| 2014 | 16 | 17 |
| 2015 | 25 | 15 |
| 2016 | 10 | 11 |
| 2017 | 16 | 11 |
| 2018 | 15 | 11 |
| 2019 | 11 | 7 |
| 2020 | 12 | 10 |
| 2021 | 8 | 23 |
| 2022 | 17 | 16 |
| 2023 | 19 | 19 |
| 2024 | 21 | 16 |
| 2025 | 18 | 16 |
| 2026 | 6 | 16 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
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- Optimization of pipeline communication buses in data transfer architectures27 Aug 2026US 2026/0252516 A1QUALCOMM Incorporated
- Interface device and method of operating the same27 Aug 2026US 2026/0252524 A1SK hynix Inc.
- Device and computing system including the device27 Aug 2026US 2026/0254606 A1SK hynix Inc.
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Most cited
By later US patents
- Storage router and method for providing virtual local storage495US 5,941,972 ACrossroads Systems, Inc. · 1999
- Storage router and method for providing virtual local storage282US 6,425,035 B1Crossroads Systems, Inc. · 2002
- Multiple class memory systems214US 8,930,647 B1P4Tents1, LLC · 2015
- Distributed read and write caching implementation for optimized input/output applications179US 6,681,292 B2Intel Corporation · 2004
- System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair151US 6,073,190 AMicron Electronics, Inc. · 2000