Distributed read and write caching implementation for optimized input/output applications

A caching input/output system, comprising:

• a host interface to connect with a host;
• at least one input/output interface;
• at least one input/output device connected with the input/output interface;
• a write cache to manage memory writes initiated by the input/output device;
• at least one read cache, separate from the write cache, to provide a low-latency copy of data that is most likely to be used, wherein the at least one read cache is in communication with the write cache;
• and
• a cache directory to track cache lines in the write cache and the at least one read cache, wherein the cache directory is in communication with the write cache and the at least one read cache.

A caching input/output system, comprising:

• a coherent host interface;
• a coherent host connected with the coherent host interface;
• a first input/output interface;
• a second input/output interface;
• a first input/output device connected with the first input/output interface;
• a second input/output device connected with the second input/output interface;
• a write cache to manage coherent memory writes initiated by at least one of the first input/output device and the second input/output device;
• at least one read cache, separate from the write cache, to provide a low-latency copy of data that is most likely to be used, wherein the at least one read cache is in communication with the write cache;
• and
• a cache directory to track cache lines in the write cache and the at least one read cache, wherein the cache directory is in communication with the write cache and the at least one read cache.

A caching input/output system, comprising:

• a coherent host interface;
• a coherent host connected with the coherent host interface;
• a first input/output interface;
• a second input/output interface;
• a first input/output device connected with the first input/output interface;
• a second input/output device connected with the second input/output interface;
• a write cache to manage coherent memory writes initiated by at least one of the first input/output device and the second input/output device;
• a first read cache separate from the write cache and associated with the first input/output interface;
• a second read cache separate from the write cache and associated with the second input/output interface, wherein the first read cache and the second read cache provide a low-latency copy of data that is most likely to be used, and the first read cache and the second read cache are in communication with the write cache;
• and
• a cache directory to track cache lines in the write cache, the first read cache, and the second read cache, wherein the cache directory is in communication with the write cache, the first read cache, and the second read cache.

A computer system, comprising:

• a plurality of processor units;
• a main memory;
• a coherent interface to maintain coherency between the processor units and their caches;
• a scalability node controller interconnecting the processor units, the main memory, and the coherent interface to control interface therebetween;
• and
• a caching input/output hub in communication with the coherent interface, including:
• a host interface to connect with the coherent interface;
• at least one input/output interface to connect with an input/output device;
• a write cache to manage memory writes initiated by the input/output device;
• at least one read cache, separate from the write cache, to provide a low-latency copy of data that is most likely to be used, wherein the at least one read cache is in communication with the write cache;
• and
• a cache directory to track cache lines in the write cache and the at least one read cache, wherein the cache directory is in communication with the write cache and the at least one read cache.