System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair
AssigneeMicron Electronics, Inc.
InventorJeffrey Jay Rooney
Life of this patent
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Abstract
A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.
Claims41
A bridge circuit in a computer system for providing data transfers between a processor and a peripheral device, comprising:
- a first address buffer and a second address buffer, both in communication with a processor and a peripheral device;
- a first data buffer and a second data buffer, both in communication with said processor, and said peripheral device;
- control logic for controlling said first address buffer and said first data buffer as a matched pair so that an address held in said first address buffer corresponds to data held in said first data buffer and to allow data to be read from said first data buffer while an address is written to said first address buffer;
- and
- an arbiter for controlling concurrent bi-directional data flow between said processor and said peripheral device through said second buffer.
In a computer system, a dynamic buffer system for controlling data flow between a processor and a Peripheral Component Interconnect (PCI) device, comprising:
- a first address buffer in communication with a processor and a PCI device;
- a first data buffer in communication with said processor, said PCI device and said first buffer;
- control logic controlling said first address buffer and said first data buffer as matched pairs so that an address stored in said first address buffer corresponds to data stored in said first data buffer and configured to allow data to be read from said first data buffer while an address is written to said first address buffer;
- and
- an arbiter for controlling bi-directional data flow between said processor and said PCI device, wherein said data is buffered by said second buffer.
In a computer system including a processor and a peripheral device, a dynamic buffer system for controlling data flow between a processor and a peripheral device, comprising:
- a plurality of address buffers in communication with said processor and said peripheral device;
- a plurality of bi-directional data buffers in communication with said processor, said peripheral device and said address buffer, each of said data buffers being associated with one of said address buffers;
- control logic configured to allow data to be transferred from one of said data buffers to said processor while data is being transferred from another of said data buffers to said peripheral device;
- and
- an arbiter for controlling bi-directional data flow between said processor and said peripheral device, wherein said data is buffered by said data buffer.
A bridge circuit for controlling substantially concurrent data transfers between a processor and a peripheral device in a computer system, comprising:
- means for buffering address requests from said processor to said peripheral device;
- means for bi-directionally buffering data transfers between said processor and said peripheral device;
- and
- control logic for controlling said means for buffering and said means for bidirectionally buffering so that each of said buffered data transfers relates to an address held in said means for buffering.
In a computer system including a processor and a peripheral device, an integrated circuit for controlling data flow between a processor and a peripheral device, comprising:
- a processor bus master controller;
- a processor bus slave controller;
- and
- a dynamic allocation system in communication with said processor bus master controller and said processor bus slave controller, the dynamic allocation system comprising:
- an address buffer in communication with said processor and said peripheral device;
- a bi-directional data buffer in communication with said processor, said peripheral device and said address buffer;
- control logic for controlling said address buffer and said data buffer as matched pairs so that an address stored in an address buffer corresponds to data stored in said data buffer and for controlling bi-directional data flow between said processor and said peripheral device, wherein said data is buffered by said data buffer.
A bi-directional buffer for transferring address and data between components of a computer system comprising:
- a first buffer in communication with a first component for storing an address, said first buffer including status bits;
- a second buffer, matched with said first buffer so that said address stored in said first buffer is related to data stored in said second buffer;
- an arbiter in communication with said status bits, said arbiter providing signals granting concurrent access to said first buffer and said second buffer such that data can be written to said first buffer while data is read from said second buffer.
Dependencies are inferred from the claim text.