G06F 11/1056
Updating check bits on partial write, i.e. read/modify/write
Official title: {Updating check bits on partial write, i.e. read/modify/write}
G06F11/1056 (Updating check bits on partial write, i.e. read/modify/write) appears on 112 US grants and 79 published applications in this corpus.
Search patents in G06F- Granted patents
- 112
- Published applications
- 79
- Assignees
- 51
- Inventors
- 245
- Latest grant
- 18 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 2 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 4 | 0 |
| 1990 | 1 | 0 |
| 1991 | 3 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 3 | 0 |
| 1995 | 2 | 0 |
| 1996 | 2 | 0 |
| 1997 | 2 | 0 |
| 1998 | 2 | 0 |
| 1999 | 4 | 0 |
| 2000 | 2 | 0 |
| 2001 | 0 | 0 |
| 2002 | 1 | 0 |
| 2003 | 0 | 0 |
| 2004 | 1 | 1 |
| 2005 | 1 | 0 |
| 2006 | 0 | 2 |
| 2007 | 1 | 0 |
| 2008 | 2 | 1 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 1 | 2 |
| 2012 | 2 | 2 |
| 2013 | 1 | 3 |
| 2014 | 1 | 3 |
| 2015 | 4 | 3 |
| 2016 | 3 | 3 |
| 2017 | 3 | 6 |
| 2018 | 8 | 7 |
| 2019 | 6 | 9 |
| 2020 | 10 | 11 |
| 2021 | 14 | 6 |
| 2022 | 3 | 5 |
| 2023 | 6 | 3 |
| 2024 | 5 | 5 |
| 2025 | 2 | 4 |
| 2026 | 4 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Methods, apparatuses, and systems for managing parity data generation in a memory system18 Aug 2026US 12,711,012 B2Yangtze Memory Technologies Co., Ltd.
- Error rates for memory with built in error correction and detection18 Aug 2026US 12,711,013 B2Microsoft Technology Licensing, LLC
- Maintaining integrity of configuration data for memory systems4 Aug 2026US 12,699,628 B2Micron Technology, Inc.
- Semiconductor device with user defined operations and associated methods and systems28 Apr 2026US 12,613,770 B2
- Erroneous bit discovery in memory system8 Jul 2025US 12,353,280 B2
- Semiconductor device with user defined operations and associated methods and systems10 Sep 2026US 2026/0267734 A1Lodestar Licensing Group LLC
- In-vehicle network system and management method of in-vehicle network system26 Feb 2026US 2026/0056835 A1Denso Corporation
- Methods, apparatuses, and systems for managing parity data generation in a memory system5 Feb 2026US 2026/0037376 A1Yangtze Memory Technologies Co., Ltd.
- Optimized error correction code architecture for memory27 Nov 2025US 2025/0362999 A1Arm Limited
- Erroneous bit discovery in memory system30 Oct 2025US 2025/0335293 A1Lodestar Licensing Group LLC
Most cited
By later US patents
- Method and apparatus for automatically scrubbing ECC errors in memory via hardware198US 6,101,614 AIntel Corporation · 2000
- Memory card, computer system and method of operation for differentiating the use of read-modify-write cycles in operating and initializaiton modes154US 5,488,691 AInternational Business Machines Corporation · 1996
- Smart memory card architecture and interface142US 4,888,773 AInternational Business Machines Corporation · 1989
- ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme113US 5,313,475 AInternational Business Machines Corporation · 1994
- ECC in memory arrays having subsequent insertion of content87US 6,009,547 AInternational Business Machines Corporation · 1999