US 4,888,773 AGranted

Smart memory card architecture and interface

AssigneeInternational Business Machines Corporation

InventorsDavid L. Arlington, Jacqueline M. Cole, Bruce G. Hazelzet, David J. Krolak, Hehching H. Li, Bharat J. Oza, A. Frank Weaver

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Abstract

A "smart" memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide seminconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the "smart" memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.

Claims11

Dependent claims

An improved smart memory card architecture of the type including a memory array communicating with a system bus via on-card logic, said on-card logic comprising:

first latch means connected to receive data from said memory array for temporarily storing said data;
error correction code means connected to receive data from said first latch means for performing error detection and correction on said data;
second latch means connected to receive data from said error correction code means for temporarily storing said data;
and
data output select means connected to receive data from said error correction code means and said second latch means for selectively transmitting data to said system bus;
wherein said first latch means, said error correction code means and said second latch means each comprise odd and even parts, said data output select means being connected to receive data from both odd and even parts of said error correction code means and said second latch means, said on-card logic further comprising control means for controlling said data select means to interleave data from said odd and even parts.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/206,757Filed 15 Jun 1988
Granted: 19 Dec 1989
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 11/106
Using arrangements adapted for a specific error detection or correction feature: correcting systematically all correctable errors, i.e. scrubbing
G06F 11/1028
Using codes or arrangements adapted for a specific type of error: adjacent errors, e.g. error in n-bit wide storage units, i.e. package error
G06F 11/1056
Using arrangements adapted for a specific error detection or correction feature: updating check bits on partial write, i.e. read/modify/write
G06F
Computing and data processing