US 5,313,475 AGranted

ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme

AssigneeInternational Business Machines Corporation

InventorsDaryl C. Cromer, Gene J. Gaudenzi, Paul C. King, Kevin G. Kramer, Timothy J. Louie

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Abstract

An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.

Claims11

Dependent claims

A computer system comprising:

a processor and a plurality of components connected to a system bus;
a memory connected to a memory bus;
means interfacing said system and memory buses, said processor and said components communicating in words composed of differing numbers of bytes over said system bus, said interfacing means including error checking and correcting logic connected to said memory bus and providing a partial write function that permits a read/modify/write operation, said interfacing means comprising:
a first receiver connected to said memory bus for receiving data bits and check bits read out of said memory;
a first driver connected to said memory bus for transferring data bits and check bits from the system bus to said memory;
a second receiver connected to said system bus for receiving data bits from said processor and components, said first driver being connected to said second receiver;
a second driver connected to said system bus for transferring data bits to said processor and components;
said error checking and correcting logic connected to said first and second receiver for receiving data bits and check bits and generating corrected data bits and corrected check bits, said first driver being connected to receive said corrected check bits from said error checking and correcting logic, said error checking and correcting logic generating a first error flag upon the detection and correction of a single bit error and a multiple error flag upon the detection of multiple bit errors;
an internal receiver connected to receive corrected data bits from said error checking and correcting logic and supplying said corrected data bits to said second driver;
and
an internal bus connected to said internal receiver and to said second receiver for transferring corrected data bits subject to a partial write function to said memory via said first driver, said internal receiver being active for all bytes of data that are not changing and said second receiver being active for all bytes of data that are changing during a partial write so as to allow desired bits to appear on said internal bus.

8 more elements

A computer system comprising:

a processor and a plurality of components connected to a system bus;
a memory connected to a memory bus;
means interfacing said system and memory buses, said interfacing means including error checking and correcting logic connected to said memory bus, said interfacing means comprising:
a first receiver connected to said memory bus for receiving data bits and check bits read out of said memory;
a first driver connected to said memory bus for transferring data bits and check bits from said system bus to said memory;
a second receiver connected to said system bus for receiving data bits and parity bits from said processor and components;
and
a second driver connected to said system bus for transferring data bits form said memory bus to said processor and components;
said error checking and correcting logic being connected to said first and second receivers for receiving data bits, check bits and parity bits and generating corrected data bits, corrected check bits and corrected parity its, said error checking and correcting logic generating a first error flag upon the detection and correction of a single bit error and a multiple error flag upon the detection of multiple bit errors, said error checking and correction logic comprising a plurality of Exclusive OR trees, at least some of which generate both check bits and parity bits according to a predetermined error correcting code.

6 more elements

Dependencies are inferred from the claim text.