Error rates for memory with built in error correction and detection
AssigneeMicrosoft Technology Licensing, LLC
InventorMonish Shah
Life of this patent
Estimating the term…
Abstract
The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank uses one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.
Claims20
A method, comprising:
- receiving a read request for data, wherein a subset of a plurality of memory chips with built in error detection stores the data;
- receiving in response to the read request, the data from the subset of the memory chips;
- receiving parity bits, wherein one memory chip in the plurality of memory chips, different from the subset of the memory chips, stores the parity bits;
- receiving an indication from any of the built in error detection of the plurality of memory chips that an uncorrectable error (UE) occurred in the data;
- and
- rebuilding corrupted data by performing an exclusive OR operation using the parity bits by adding a one or a zero for a bit to result in an even parity where an even number of inputs are true in response to the exclusive OR operation.
A system, comprising:
- a plurality of memory chips with built in error detection, wherein a subset of the memory chips stores data and one memory chip different from the subset of the memory chips stores parity bits;
- and
- a memory controller in communication with the plurality of memory chips, wherein the memory controller is operable to:
- receive a read request for data;
- receive in response to the read request, the data from the subset of the memory chips;
- receive parity bits, wherein one memory chip in the plurality of memory chips, different from the subset of the memory chips, stores the parity bits;
- receive an indication from any of the built in error detection of the plurality of memory chips that an uncorrectable error (UE) occurred in the data;
- and
- rebuild corrupted data by performing an exclusive OR operation using the parity bits by adding a one or a zero for a bit to result in an even parity where an even number of inputs are true in response to the exclusive OR operation.
A system, comprising:
- a plurality of memory chips with built in error detection, wherein a subset of the memory chips stores data and one memory chip different from the subset of the memory chips stores parity bits;
- and
- a memory controller in communication with the plurality of memory chips, wherein the memory controller is operable to:
- receive a read request for data;
- receive the data from the subset of the memory chips;
- receive parity bits from the one memory chip different from the subset of the memory chips;
- verify that an error notification was not received from the subset of the memory chips;
- and
- verify whether a silent data corruption occurred in the data in any of the plurality of memory chips using the parity bits in a parity check.
Dependencies are inferred from the claim text.