G06F 11/0745
In an input/output transactions management context
Official title: {in an input/output transactions management context (input/output processing in general G06F13/00)}
G06F11/0745 (In an input/output transactions management context) appears on 916 US grants and 854 published applications in this corpus.
Search patents in G06F- Granted patents
- 916
- Published applications
- 854
- Assignees
- 309
- Inventors
- 2,033
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 0 | 0 |
| 1978 | 3 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 3 | 0 |
| 1984 | 3 | 0 |
| 1985 | 3 | 0 |
| 1986 | 3 | 0 |
| 1987 | 4 | 0 |
| 1988 | 3 | 0 |
| 1989 | 3 | 0 |
| 1990 | 8 | 0 |
| 1991 | 2 | 0 |
| 1992 | 2 | 0 |
| 1993 | 5 | 0 |
| 1994 | 5 | 0 |
| 1995 | 8 | 0 |
| 1996 | 4 | 0 |
| 1997 | 11 | 0 |
| 1998 | 10 | 0 |
| 1999 | 13 | 0 |
| 2000 | 8 | 0 |
| 2001 | 15 | 1 |
| 2002 | 9 | 16 |
| 2003 | 6 | 14 |
| 2004 | 14 | 19 |
| 2005 | 10 | 30 |
| 2006 | 15 | 25 |
| 2007 | 16 | 15 |
| 2008 | 27 | 26 |
| 2009 | 23 | 32 |
| 2010 | 29 | 15 |
| 2011 | 29 | 25 |
| 2012 | 28 | 28 |
| 2013 | 22 | 39 |
| 2014 | 40 | 50 |
| 2015 | 41 | 70 |
| 2016 | 65 | 56 |
| 2017 | 50 | 38 |
| 2018 | 36 | 41 |
| 2019 | 44 | 52 |
| 2020 | 54 | 36 |
| 2021 | 48 | 32 |
| 2022 | 34 | 32 |
| 2023 | 29 | 41 |
| 2024 | 52 | 58 |
| 2025 | 45 | 39 |
| 2026 | 28 | 24 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Correctable error tracking and link recovery6 Oct 2026US 12,754,803 B2Intel Corporation
- Method for managing the isolation of resources of a system-on-chip, and corresponding system-on-chip22 Sep 2026US 12,743,329 B2STMicroelectronics (Grand Ouest) SAS
- Bus error management method8 Sep 2026US 12,730,699 B2STMicroelectronics International N. V.
- Transaction exchange platform with a validation microservice for validating transactions before being processed18 Aug 2026US 12,711,513 B2Capital One Services, LLC
- Low latency post-send7 Jul 2026US 12,675,354 B2NVIDIA Corporation
- Method and apparatus for repairing call chain, device, and product1 Oct 2026US 2026/0300083 A1Beijing Zitiao Network Technology Co., Ltd.
- Low latency post-send24 Sep 2026US 2026/0288555 A1NVIDIA Corporation
- Transaction Exchange Platform with Messaging and Watchdog Microservices17 Sep 2026US 2026/0278616 A1Capital Ome Services, LLC
- Device to connect a no-post/no-video information handling system to a remote server3 Sep 2026US 2026/0259790 A1Dell Products L. P.
- Fault resilient transaction handling device3 Sep 2026US 2026/0259793 A1Mellanox Technologies, Ltd.
Most cited
By later US patents
- PCI hot spare capability for failed components188US 5,864,653 ACompaq Computer Corporation · 1999
- Error recovery by isolation of peripheral components in a data processing system169US 5,815,647 AInternational Business Machines Corporation · 1998
- Addressable shadow port and protocol for serial bus networks133US 5,483,518 ATexas Instruments Incorporated · 1996
- Apparatus of fault-handling in a multiprocessing system122US 4,438,494 AIntel Corporation · 1984
- System and method for using hot plug configuration for PCI error recovery122US 7,447,934 B2International Business Machines Corporation · 2008