Bus error management method
AssigneeSTMicroelectronics International N.V.
InventorJawad Benhammadi
Life of this patent
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Abstract
The present description concerns a bus error management method, wherein one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge, are stored, and wherein in the presence of a bus error sent by the functional unit: one or a plurality of second characteristics linked to said error are stored; the bridge generates a first interrupt that it transmits with said first and second characteristics to a management unit; and the management unit generates at least one second interrupt intended for a processing unit as a function of the first and/or second characteristics.
Claims15
A bus error management method, comprising
- storing one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge;
- and in the presence of a bus error sent by the functional unit:
- storing one or a plurality of second characteristics linked to the error;
- generating, by the bridge, a first interrupt that it transmits with the first characteristics and second characteristics to a management unit;
- and
- generating, by the management unit, at least one second interrupt intended for a processing unit as a function of at least one of the first or second characteristics,
- wherein the management unit stores the first characteristics and second characteristics after the transmission of the first interrupt and of the first characteristics and second characteristics by the bridge.
A microcontroller comprising at least one control unit, a bridge, a functional unit, and a management unit;
- the microcontroller being configured to:
- store one or a plurality of first characteristics of a first write transaction intended for the functional unit and transiting through the bridge;
- and
- in the presence of a bus error sent by the functional unit:
- the bridge generates a first interrupt that it transmits with the first characteristics and second characteristics to the management unit;
- and
- the management unit generates at least one second interrupt intended for a processing unit as a function of at least one of the first or second characteristics,
- wherein the management unit stores the first characteristics and second characteristics after the transmission of the first interrupt and of the first characteristics and second characteristics by the bridge.
A bus error management method, comprising:
- storing one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge;
- and in the presence of a bus error sent by the functional unit:
- storing one or a plurality of second characteristics linked to the error;
- generating, by the bridge, a first interrupt that it transmits with the first and second characteristics to a management unit;
- and
- generating, by the management unit, at least one second interrupt intended for a processing unit as a function of at least one of the first or second characteristics, wherein the first characteristics and second characteristics are stored in one or a plurality of registers of the management unit and wherein the management unit performs at least one of:
- storing the first and second characteristics in registers having an access restriction level similar to an access restriction level associated with the first characteristics, or transmitting the second interrupt to the processing unit having an access restriction level similar to the access restriction level associated with the first characteristics.
Dependencies are inferred from the claim text.