NPTest, LLC
San Jose, CA, US· latest recorded location
NPTest, LLC is named on 17 US grants and 14 published applications in this corpus. Its most frequent classification is G01R (Measuring electric variables).
- Granted patents
- 17
- Published applications
- 14
- Inventors
- 36
- Granted in 2026 so far
- 0
- Most recent grant
- 6 Sep 2005
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2002 | 0 | 3 |
| 2003 | 4 | 5 |
| 2004 | 9 | 6 |
| 2005 | 4 | 0 |
By publication year.
Technology areas
Share of 31 documents
- G01RMeasuring electric variables23
- H10PGeneric processes or apparatus for the manufacture or treatment of devices covered8
- H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by5
- H01JElectric discharge tubes or discharge lamps3
- B24BMachines, devices, or processes for grinding or polishing1
- G11CStatic stores1
- H03MCoding1
- H04LDigital communication1
Recent patents
- Pin electronics interface circuit6 Sep 2005US 6,940,271 B2
- Measuring back-side voltage of an integrated circuit29 Mar 2005US 6,872,581 B2
- Method and apparatus for forming a cavity in a semiconductor substrate using a charged particle beam15 Feb 2005US 6,855,622 B2
- Open-loop for waveform acquisition8 Feb 2005US 6,853,941 B2
- Comparator circuit for differential swing comparison and common-mode voltage comparison23 Nov 2004US 6,822,435 B2
- Very small pin count IC tester23 Sep 2004US 2004/0187049 A1
- Method and apparatus for accessing internal nodes of an integrated circuit using ic package substrate9 Sep 2004US 2004/0173878 A1
- Method for surface preparation to enable uniform etching of polycrystalline materials6 May 2004US 2004/0084407 A1
- Method for surface preparation to enable uniform etching of polycrystalline materials6 May 2004US 2004/0084408 A1
- Apparatus and method for contacting device with delicate light-transparent pane6 May 2004US 2004/0084765 A1
Most cited
By later US patents
- Measuring jitter of high-speed data channels62US 6,661,836 B12003
- Test system and methodology23US 6,744,267 B22004
- Scan stream sequencing for testing integrated circuits18US 6,748,564 B12004
- Method for global die thinning and polishing of flip-chip packaged integrated circuits17US 6,672,947 B22004
- Pin electronics interface circuit13US 6,940,271 B22005