Very small pin count IC tester

A system for testing a semiconductor device with the help of a tester device, the system comprising:

• a. a first circuit in the tester device to produce test related data;
• b. a clock generator in the tester device to generate clock signals;
• c. a first transmission line between the tester device and the semiconductor device, the first transmission line capable of carrying clock signals from the tester device to the semiconductor device, the clock signals being generated by the clock generator;
• d. a second transmission line between the tester device and the semiconductor device, the second transmission line capable of carrying test related data between the tester device and the semiconductor device;
• e. a first transceiver in the tester device capable of simultaneously transmitting and receiving test related data over the second transmission line, the transmission and reception of test related data being synchronized with the clock signals;
• and
• f. a second transceiver in the semiconductor device, the second transceiver capable of simultaneously transmitting and receiving test related data over the second transmission line, the transmission and reception of test related data being synchronized with the clock signals.

A method for testing a semiconductor device with the help of a tester device, the semiconductor device comprising a first transceiver for sending and receiving test related data, the tester device comprising a second transceiver, a test circuit and a clock generator, the method comprising the steps of:

• a. connecting a first transmission line between the tester device and the semiconductor device, the first transmission line capable of carrying clock signals from the tester device to the semiconductor device, the clock signals being generated by the clock generator;
• b. connecting a second transmission line between the tester device and the semiconductor device, the second transmission line capable of carrying test related data between the tester device and the semiconductor device;
• c. synchronizing transmission and reception of test related data by the tester device with the clock signals generated by the clock generator;
• and
• d. simultaneously sending and receiving test related data over the second transmission line between the tester device and the semiconductor device, the transmission and reception of test related data being synchronized with the clock signals.