Intergrated Device Technology, Inc.
San Jose, CA, US· latest recorded location
Intergrated Device Technology, Inc. is named on 9 US grants and 3 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 9
- Published applications
- 3
- Inventors
- 24
- Granted in 2026 so far
- 0
- Most recent grant
- 2 Jun 2020
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2000 | 1 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 1 | 0 |
| 2007 | 0 | 1 |
| 2008 | 1 | 0 |
| 2009 | 1 | 0 |
| 2010 | 0 | 0 |
| 2011 | 1 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 1 |
| 2014 | 0 | 1 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 1 | 0 |
| 2018 | 1 | 0 |
| 2019 | 0 | 0 |
| 2020 | 1 | 0 |
By publication year.
Technology areas
Share of 12 documents
- G06FComputing and data processing7
- H04LDigital communication4
- G11CStatic stores3
- H03GControl of amplification2
- H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or1
- Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1
Recent patents
- Command sequence response in a memory data buffer2 Jun 2020US 10,671,300 B1
- Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system2 Jan 2018US 9,860,088 B1
- Low noise variable gain amplifier utilizing variable feedback techniques with constant input/output impedance26 Dec 2017US 9,853,616 B2
- Behavioral modeling of high speed differential signals based on physical characteristics18 Oct 2011US 8,041,552 B2
- Method and apparatus for generating a random bit stream in true random number generator fashion8 Sep 2009US 7,587,439 B1
- Low noise variable gain amplifier utilizing variable feedback techniques with constant input/output impedance30 Oct 2014US 2014/0320207 A1
- Systems and methods for peak detection in automatic gain control circuits in high-speed wireline communications12 Sep 2013US 2013/0235955 A1
- Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits7 Jun 2007US 2007/0130246 A1
Most cited
By later US patents
- Dynamic phase-locked loop circuits and methods of operation thereof38US 7,046,093 B12006
- Method and apparatus for generating a random bit stream in true random number generator fashion12US 7,587,439 B12009
- Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system7US 9,860,088 B12018
- Apparatus and method for recording a floating point error pointer in zero cycles6US 6,014,743 A2000
- Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits5US 7,356,722 B22008