Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system
AssigneeIntergrated Device Technology, Inc.
InventorsCraig DeSimone, Praveen Singh, Alejandro Gonzalez, Yue Yu, YanBo Wang
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Abstract
An apparatus includes a detector circuit and a data buffer. The detector circuit may be configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with the start of the command sequence. The data buffer circuit may be configured to initialize a condition of a receiver circuit in response to the control signal prior to reception of a first data bit associated with the command sequence.
Claims20
An apparatus comprising:
- a detector circuit configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with said start of said command sequence;
- and
- a data buffer circuit configured to initialize a receiver circuit by setting one or more taps of a decision feedback equalizer (DFE) of said receiver circuit to match a quiescent VDD termination level in response to said control signal prior to reception of a first data bit associated with said command sequence.
A method of initializing a receiver circuit comprising:
- identifying a start of a command sequence associated with a directed access to a memory system;
- generating a control signal indicating a non-consecutive clock associated with said start of said command sequence;
- and
- initializing said receiver circuit by setting one or more taps of a decision feedback equalizer (DFE) of said receiver circuit to match a quiescent VDD termination level in response to said control signal prior to reception of a first data bit associated with said command sequence.
Dependencies are inferred from the claim text.