Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits
AssigneeIntergrated Device Technology, Inc.
InventorsOnchuen (Daryn) Lau, Matthew Ornes, Chris Bergen, Robert Divivier, Gene Chui, Christopher Norrie, King-Shing (Frank) Chui
Life of this patent
Estimating the term…