Dynamic phase-locked loop circuits and methods of operation thereof
AssigneeIntergrated Device Technology, Inc.
InventorsDeclan McDonagh, Paul Murtagh
Life of this patent
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AssigneeIntergrated Device Technology, Inc.
InventorsDeclan McDonagh, Paul Murtagh
Estimating the term…
A phase locked loop (PLL) circuit includes a controlled oscillator circuit that is operative to generate an output clock signal responsive to an oscillator control signal according to a plurality of selectable transfer functions, and an oscillator control signal generator circuit that is operative to generate the oscillator control signal responsive to the output clock signal and a reference clock signal. The PLL circuit further includes a transfer function control circuit operative to transition operation of the controlled oscillator from a first one of the transfer functions to a second one of the transfer functions responsive to the oscillator control signal. For example, the transfer function control circuit may step the controlled oscillator circuit through a succession of the transfer functions in response to a change in a frequency of the reference clock signal and may enable a closed loop including the oscillator control signal generator circuit and the controlled oscillator circuit upon selection of each of the succession of transfer functions.
A phase locked loop (PLL) circuit, comprising:
A PLL circuit, comprising:
A method of operating a PLL circuit including a controlled oscillator that produces an output clock signal having a frequency that varies according to an oscillator control voltage wherein the PLL circuit comprises a loop filter and a charge pump circuit operative to charge and discharge the loop filter responsive to the output clock signal and a reference clock signal to generate the oscillator control voltage, the method comprising:
Dependencies are inferred from the claim text.