Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits
AssigneeIntergrated Device Technology, Inc.
InventorsOnchuen (Daryn) Lau, Matthew D. Ornes, Chris D. Bergen, Robert J. Divivier, Gene K. Chui, Christopher I. W. Norrie, King-Shing (Frank) Chui
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