Efficient Memory Technology
Rochester, MN, US· latest recorded location
Efficient Memory Technology is named on 4 US grants and 4 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 4
- Published applications
- 4
- Inventors
- 1
- Granted in 2026 so far
- 0
- Most recent grant
- 29 May 2012
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2008 | 0 | 1 |
| 2009 | 0 | 1 |
| 2010 | 2 | 2 |
| 2011 | 1 | 0 |
| 2012 | 1 | 0 |
By publication year.
Technology areas
Share of 8 documents
Recent patents
- Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines29 May 2012US 8,190,809 B2
- Intelligent memory banks for storing vectors6 Dec 2011US 8,074,010 B2
- Method and apparatus of multiple abbreviations of interleaved addressing of paged memories17 Aug 2010US 7,779,198 B2
- Result data forwarding in parallel vector data processor based on scalar operation issue order9 Feb 2010US 7,660,967 B2
- Intelligent memory banks for storing vectors9 Dec 2010US 2010/0312945 A1
- Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines3 Jun 2010US 2010/0138587 A1
- Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor12 Feb 2009US 2009/0043943 A1
- Vector processing7 Aug 2008US 2008/0189513 A1
Most cited
By later US patents
- Result data forwarding in parallel vector data processor based on scalar operation issue order9US 7,660,967 B22010
- Intelligent memory banks for storing vectors7US 8,074,010 B22011
- Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines7US 8,190,809 B22012
- Method and apparatus of multiple abbreviations of interleaved addressing of paged memories3US 7,779,198 B22010