Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines

Apparatus for addressing a memory of a computer system, the memory containing individually and successively addressable memory banks, where is an integer, each memory bank having a plurality of individually and successively addressable data storage locations for storing data, the apparatus comprising:

• a bank select device for choosing bank selects for addressing the memory banks in an offset interleaved pattern, the bank select device comprising
• a plurality of addressable locations, and
• a plurality of storage locations, each storage location being correlated to a respective one or more of the plurality of addressable locations and each addressable location being correlated to one of the plurality of storage locations, each storage location containing a respective bank select for addressing a respective one of the addressable memory banks, there being at least as many storage locations as there are addressable storage data locations in one memory bank,
• the addressable locations and storage locations being grouped into a plurality of interleave patterns such that, for each interleave pattern, there are Q storage locations and there are 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A, 0<R<Q, ≧Q≧3 and Q has at least one odd factor greater than 1, and where A, L, Q and R are integers,
• a shunt having a value, S, defining an offset for each interleave pattern so that each interleave pattern of the plurality of interleave patterns commences with a different bank select and a complete rotation of all of the interleave patterns addresses each of the memory banks an equal number of times,
• the bank select device being responsive to an input address to an addressable location to choose the bank select from the correlated storage location, such that successive input addresses to successive address locations during execution of a respective interleave pattern choose successive bank selects, the plurality of interleave patterns being organized so that bank selects are chosen to address a different set of Q memory banks during execution of different ones of the plurality of interleave patterns, and execution of a complete rotation of the plurality of interleave patterns addresses all of the plurality of memory banks;
• and
• address apparatus responsive to the bank select device to address successive memory banks using the chosen successive banks selects.