Method and apparatus of multiple abbreviations of interleaved addressing of paged memories

A computer process for selectively addressing a memory containing a plurality of memory banks having H address logic states, where H is an integer greater than 1, comprising steps of:

• defining a plurality of interleave patterns in a bank select device having a plurality of storage locations and a plurality of addressable locations, each interleave pattern for choosing bank selects for addressing Q memory banks and each interleave pattern having addressable locations, Q storage locations each containing a respective bank select, L sequential loops of Q sequentially addressable locations and a remainder loop of R sequentially addressable locations, where L·Q+R=2A, 0<R<Q and A, L, Q and R are integers and Q is greater than 1, smaller than the number of addressable memory banks and has no non-unitary factor common to H,
• the step of defining interleave patterns comprising, for each pattern, steps of
• correlating
• each of the sequentially addressable locations in each of the loops to a storage location containing a respective one of the bank selects,
• each of the storage locations containing a bank select to a respective one addressable location in each of the L loops, and
• R of the storage locations containing a bank select to respective ones of the R addressable locations in the remainder loop;
• executing interleave patterns in response to an input address to successively address addressable locations in one or more of the plurality of interleave patterns to choose respective successive bank selects;
• and
• addressing the memory banks with the chosen bank selects, the plurality of interleave patterns being offset from each other such that a different set of Q memory banks are addressed by execution of different ones of the plurality of interleave patterns.

A process of constructing a bank select device for addressing a plurality of memory banks of a computer system, comprising steps of:

• defining a plurality of interleave patterns in bank select device having a plurality of storage locations and a plurality of addressable locations, each interleave pattern having
• Q storage locations, each containing a respective bank select,
• L sequential loops of Q sequentially addressable locations, and
• a remainder loop of R sequentially addressable locations,
• where L·Q+R=2A, 0<R<Q, 3Q<2B, A, B, L and R are integers and Q is an odd integer greater than 1 and smaller than the number of addressable memory banks;
• correlating
• each of the sequentially addressable locations in each of the loops to a storage location containing a respective one of the bank selects,
• each of the storage locations to a respective one addressable location in each of the L loops, and
• R of the storage locations containing a bank select to respective ones of the R addressable locations in the remainder loop;
• and
• offsetting the plurality of interleave patterns from each other such that a different set of Q memory banks are addressed by execution of different ones of the plurality of interleave patterns.