Result data forwarding in parallel vector data processor based on scalar operation issue order

A computer system comprising:

• a memory having a plurality of addressable storage locations for storing data-elements;
• a cache selectively coupled to the memory to read cache-lines containing data-elements from the memory and to write cache-lines containing data-elements to the memory, each cache-line containing data-elements arranged such that at least some data-elements of a cache-line may be vector data-elements;
• and
• a processor responsive to vector defining instructions to issue successive scalar processing instructions in an issue order to successively process data-elements of first and second vectors to generate result data-elements, the first vector comprising a plurality of successive first data-elements arranged in a vector order and the second vector comprising a plurality of successive second data-elements arranged in the vector order,
• the processor comprising:
• a plurality of functional units, each functional unit being responsive to the scalar processing instructions for pipelined execution of a selected function on respective first and second data-elements as a pair of operands to generate a respective result data-element, at least one of the functional units being selectively coupled to the cache to receive data-elements from the cache and to transfer result data-elements to cache-lines in the cache, at least some of the functional units requiring different periods of execution;
• a first architectural register having input-vector capability coupled to the memory to receive successive first data-elements in vector order, a second architectural register having input-vector capability coupled to the memory to receive successive second data-elements in vector order, at least a third architectural register having output-vector capability coupled to the memory to selectively write result data-elements to the memory, at least each of the architectural registers having output-vector capability being coupled to the plurality of functional units to transfer data-elements as operands to selected functional units and to receive result data-elements from a selected functional unit;
• a plurality of result registers each coupled to a respective one of the plurality of architectural registers and to the plurality of functional units to receive result data-elements from selected functional units for use as operands by subsequent processing instructions, each result register being responsive to the issuance of successive processing instructions to selectively transfer the result data-elements to the respective architectural register, or to a functional unit for further processing, or to the memory, each result register and at least each of the architectural registers capable of transferring data-elements as operands to functional units being responsive to the issuance of the successive processing instructions to transfer the data-elements as operands to the respective functional unit in the issue order,
• the processor being selectively operable to either
• i) operate the cache to load and store data-elements from the memory within one or more cache-lines, process the data-elements from a cache line to a selected functional unit for execution of a function, and process result data-elements from the functional unit to a cache-line for storing to the memory, or
• ii) by-pass the cache by operating selected architectural registers having input-vector capability to read data-elements from the memory for execution by a selected functional unit and by operating a selected architectural register having output-vector capability to write result data-elements to the memory in the issue order of the processing instructions.

A computer process for processing at least first and second regular vectors each comprising a plurality of successive data-elements in vector order to generate and store a result vector in a memory, the result vector comprising a plurality of successive result data-elements, the process comprising steps of:

• (a) writing successive data-elements of the first and second regular vectors from memory to respective first and second architectural registers without use of a cache;
• (b) issuing a plurality of successive scalar processing instructions in an issue order;
• (c) executing functions in accordance with the processing instructions on data-elements from the respective first and second architectural registers to generate respective result data-elements;
• (d) assigning issue-order codes to the result data-elements based on the issue order of the processing instructions generating the result data-elements;
• (e) selectively either executing a further function on successive result data-elements in accordance with further processing instructions or writing successive result data-elements to a third architectural register or to the memory without use of a cache;
• and
• (f) if a result data-element was transferred to third architectural register by step (e) for further processing, transferring the result data-element having an issue-order code corresponding to an issue-order code required by the further function from the first-named function or the third architectural register to the further function.