Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor

In a computer memory having a plurality of memory banks each containing a plurality of addressable memory cells, the memory being arranged to store vectors such that data elements of each vector are stored in memory cells in different memory banks in an interleaved pattern, each vector having an initial address and spacing data representing a spacing between successive addresses, the improvement comprising, for each memory bank:

• setup apparatus for receiving the initial address and spacing data for each of a plurality of vectors;
• cell select apparatus responsive to the memory for accessing a memory cell using a memory cell select associated to a respective one of the initial and successive addresses of each vector;
• and
• addressing logic responsive to the setup apparatus and the cell select apparatus for associating a memory cell select to each initial and subsequent address of each of the plurality of vectors.

Computer readable memory adapted to receive signals from a computer processor having a plurality of data storage memory banks, the computer readable memory comprising:

• a table defining a plurality of successive abbreviated interleaves, the table comprising, for each abbreviated interleave:
• L aligned rows each containing Q sequentially addressable locations, where L>1, and Q is a number greater than one and smaller than the number of data storage memory banks, and
• a memory bank select in each column for addressing one of the plurality of data storage memory banks, each memory bank select being accessible upon addressing a location in one of the rows of the corresponding column,
• the table defining the abbreviated interleaves in offset relation so that the computer processor addresses all of the plurality of data storage memory banks substantially equally when using all of the abbreviated interleaves,
• the computer readable memory being responsive to signals from the computer processor to address a row of sequentially addressable locations to select corresponding memory bank selects, the computer processor being responsive to the selected memory bank selects to address corresponding data storage memory banks for storage or retrieval of interleaved data.