Vector processing

A computer system comprising:

• a memory having a plurality of addressable storage locations for storing data-elements;
• a cache selectively coupled to the memory to read data-elements as cache-lines from the memory and to write data-elements as cache-lines to the memory, each cache-line containing data-elements arranged such that at least some data-elements of a cache-line may be vector data-elements;
• and
• a processor responsive to successive processing instructions arranged in an issue order to successively process vector data-elements of first and second vectors to generate respective result vector data-elements, the first vector comprising a plurality of successive first vector data-elements and the second vector comprising a plurality of successive second vector data-elements,
• the processor comprising:
• a plurality of functional units, each capable of performing a function on respective first and second vector data-elements as a pair of operands to generate a respective result data-element of a result vector, at least one of the functional units being selectively coupled to the cache to receive data-elements from the cache and to transfer result data-elements to cache-lines in the cache;
• a plurality of architectural registers, at least two of the architectural registers having input-vector capability and coupled to the memory to selectively receive respective data-elements, at least one of the architectural registers having output-vector capability and coupled to the memory to selectively write data-elements to the memory, the plurality of architectural registers being coupled to the plurality of functional units to transfer data-elements as operands to selected functional units and to receive result data-elements from the selected functional unit;
• a plurality of result registers each coupled to a respective one of the plurality of architectural registers and to the plurality of functional units to receive result data-elements from selected functional units, each result register being responsive to the issue order of the successive processing instructions to selectively transfer the result data-elements in issue order either to the respective architectural register for further processing by a functional unit or for output to memory, or to a functional unit for further processing, or to the memory,
• the processor being responsive to the instruction to either
• i) operate the cache to read and store vector data-elements from the memory as a cache-line, process the vector data-elements from the cache line to a selected functional unit for execution of a function, and write result data-elements from the functional unit to a cache-line for writing to the memory, or
• ii) by-pass the cache by operating selected architectural registers having input-capability to read and store vector data-elements from the memory for execution by a selected functional unit and by operating a selected architectural register having output-vector capability to write result data-elements to the memory.

A computer process for processing at least one regular vector to generate and store a result vector in a memory, the regular vector comprising a plurality of vector data-elements, the process comprising steps of:

• (a) writing successive vector data-elements from memory to designated first architectural registers without use of a cache;
• (b) issuing successive processing instructions in an issue order;
• (c) executing selected successive functions on respective vector data-elements from the respective first architectural registers to generate respective result data-elements;
• and
• (d) selectively writing successive result data-elements to the memory in the issue order without use of a cache.