H03M 13/6502
Reduction of hardware complexity or efficient processing
Official title: {Reduction of hardware complexity or efficient processing}
H03M13/6502 (Reduction of hardware complexity or efficient processing) appears on 1,011 US grants and 872 published applications in this corpus.
Search patents in H03M- Granted patents
- 1,011
- Published applications
- 872
- Assignees
- 394
- Inventors
- 1,829
- Latest grant
- 16 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 6 | 0 |
| 1995 | 16 | 0 |
| 1996 | 19 | 0 |
| 1997 | 6 | 0 |
| 1998 | 13 | 0 |
| 1999 | 26 | 0 |
| 2000 | 18 | 0 |
| 2001 | 27 | 9 |
| 2002 | 33 | 44 |
| 2003 | 36 | 47 |
| 2004 | 27 | 39 |
| 2005 | 37 | 47 |
| 2006 | 51 | 34 |
| 2007 | 45 | 39 |
| 2008 | 24 | 38 |
| 2009 | 23 | 33 |
| 2010 | 33 | 28 |
| 2011 | 34 | 37 |
| 2012 | 55 | 27 |
| 2013 | 47 | 42 |
| 2014 | 47 | 29 |
| 2015 | 37 | 40 |
| 2016 | 41 | 26 |
| 2017 | 33 | 59 |
| 2018 | 36 | 50 |
| 2019 | 65 | 42 |
| 2020 | 46 | 39 |
| 2021 | 47 | 30 |
| 2022 | 23 | 16 |
| 2023 | 18 | 22 |
| 2024 | 21 | 21 |
| 2025 | 14 | 22 |
| 2026 | 6 | 12 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Decoder scheme capable of reducing frequency of memory reading and writing during iterative decoding procedure16 Jun 2026US 12,658,942 B2Silicon Motion, Inc.
- Method and device for simplified successive cancellation list decoding of polarization-adjusted convolutional (PAC) codes9 Jun 2026US 12,652,064 B2Samsung Electronics Co., Ltd.
- Methods and procedures for polar encoding and decoding with low latency5 May 2026US 12,621,081 B2InterDigital Patent Holdings, Inc.
- Multi-channel decoder with distributed scheduling17 Feb 2026US 12,556,200 B2MaxLinear, Inc.
- Fast multi-payload-length error-correcting system and methods3 Feb 2026US 12,542,567 B2Micron Technology, Inc.
- Coding method and decoding method, coder and decoder, and chip, hard disk, and communication system30 Jul 2026US 2026/0221990 A1Cloud Intelligence Assets Holding (Singapore) Private Limited
- Decoder, and memory system for obtaining an updated posterior messages corresponding to a non-zero sub-matrix23 Jul 2026US 2026/0211809 A1Yangtze Memory Technologies Co., Ltd.
- Multi-channel decoder with distributed scheduling18 Jun 2026US 2026/0172052 A1MaxLinear, Inc.
- 5g-compatible ldpc decoder for satellite communications4 Jun 2026US 2026/0155835 A1Airbus Defence and Space GmbH
- Ldpc decoder with a multi-core architecture28 May 2026US 2026/0149467 A1Airbus Defence and Space GmbH
Most cited
By later US patents
- Methods and apparatus for decoding LDPC codes319US 6,633,856 B2Flarion Technologies, Inc. · 2003
- Apparatus, system, and method to increase data integrity in a redundant storage system200US 8,832,528 B2Fusion-Io, Inc. · 2014
- Decoding method and decoding device for a CDMA transmission system for demodulating a received signal available in serial code concatenation187US 6,377,610 B1Deutsche Telekom AG · 2002
- Reconfigurable radio system architecture185US 6,091,765 AHarris Corporation · 2000
- Viterbi decoder184US 5,923,713 ASony Corporation · 1999