Viterbi decoder

Abstract

A Viterbi decoder for reducing the access times of the path metric memory, for lowering the power consumption, speeding up the Viterbi decoding. includes a branch metric operating unit 12, an adder, comparator, selector (ASC) operating unit 13a and 13b, a path metric memory 14a for the lower states, and a path metric memory 14b for the upper states. The ACS operating unit 13a performs the ACS operation about the even states on the branch metric from the branch metric operating unit 12 and the path metric at the previous time point. The ACS operating unit 13b performs the ACS operation about the odd states. These ACS operations are executed in a time-dividing manner. The path metrics from these ACS operating units 13a and 13b are written in the path metric memories 14a and 14b. The memory 14a or 14b stores as one storage unit the path metrics of the adjacent even and odd states.

Dependencies are inferred from the claim text.