Decoder scheme capable of reducing frequency of memory reading and writing during iterative decoding procedure

A decoding method of a decoder circuit, comprising:

• using a variable node circuit to receive a specific codeword of an input data and generate or update a variable-to-check message based on data of the specific codeword and generate a log-likely ratio to a syndrome calculation circuit;
• converting the variable-to-check message from a variable node domain to a check node domain to generate a converted variable-to-check message;
• using a check node circuit to perform a minimization calculation based on the converted variable-to-check message to generate a check-to-variable message;
• converting the check-to-variable message from the check node domain to the variable node domain to generate a converted check-to-variable message;
• performing a sum calculation to update the variable-to-check message based on the converted check-to-variable message and performing another sum calculation to update the log-likely ratio;
• performing a hard decision operation based on the log-likely ratio to determine whether to flip information of at least one bit in the specific codeword to generate an output codeword;
• providing a first memory macro having multiple first physical sub-memories, to be read and written and controlled by the check node circuit to perform the minimization calculation;
• providing a second memory macro having multiple second physical sub-memories, to be read and written and controlled by the variable node circuit to perform the sum calculation and the another sum calculation;
• and
• performing a difference value calculation upon specific data to be stored in the first memory macro and a reference data to generate a difference value, activating a write operation of a portion of first physical sub-memories in the multiple first physical sub-memories to write the difference value into the portion of first physical sub-memories in the multiple first physical sub-memories, and closing a write operation of another portion of first physical sub-memories in the multiple first physical sub-memories.

A flash memory controller, comprising:

• an encoder, for performing an encoding operation upon a write data sent from a host device to write the write data into a flash memory;
• and
• a decoder circuit, for performing a decoding operation upon a read data read from the flash memory to generate a decoded data, and the decoder circuit comprises:
• a variable node circuit, for receiving a specific codeword of the read data and for generating or updating a variable-to-check message based on data of the specific codeword and generating a log-likely ratio to a syndrome calculation circuit;
• a variable-to-check circuit, coupled to the variable node circuit, for converting the variable-to-check message from a variable node domain to a check node domain to generate a converted variable-to-check message;
• a check node circuit, coupled to the variable-to-check circuit, for performing a minimization calculation based on the converted variable-to-check message to generate a check-to-variable message;
• a check-to-variable circuit, coupled to the check node circuit, for converting the check-to-variable message from the check node domain to the variable node domain to generate a converted check-to-variable message, to make the variable node circuit based on the converted check-to-variable message perform a sum calculation to update the variable-to-check message and perform another sum calculation to update the log-likely ratio;
• the syndrome calculation circuit, coupled to the variable node circuit, for performing a hard decision operation based on the log-likely ratio to determine whether to flip information of at least one bit in the specific codeword to generate an output codeword;
• a first memory macro having multiple first physical sub-memories, to be read and written and controlled by the check node circuit to perform the minimization calculation;
• and
• a second memory macro having multiple second physical sub-memories, to be read and written and controlled by the variable node circuit to perform the sum calculation and the another sum calculation;
• wherein the check node circuit performs a difference value calculation upon specific data to be stored in the first memory macro and a reference data to generate a difference value, activates a write operation of a portion of first physical sub-memories in the multiple first physical sub-memories to write the difference value into the portion of first physical sub-memories in the multiple first physical sub-memories, and closes a write operation of another portion of first physical sub-memories in the multiple first physical sub-memories.