Ldpc decoder with a multi-core architecture
AssigneeAirbus Defence and Space GmbH
InventorsLyonel BARTHE, Benjamin GADAT
Life of this patent
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Abstract
A multi-core decoder (31) for decoding low-density parity-check (LDPC) codewords. The multi-core decoder includes a group of cores (10) capable of each simultaneously decoding a different LDPC codeword. The group includes memory (20) shared between the cores (10) in which predefined Nc configurations are stored. Each predefined configuration includes a binary parity matrix corresponding to an LDPC code. Each core is suitable for being dynamically configured with any one of the Nc predefined configurations stored in the shared memory (20) to decode an LDPC codeword using a selected Nc configuration.
Claims13
A multi-core decoder for decoding low-density parity-check (LDPC) code words, wherein the multi-core decoder includes:
- at least one group of cores, wherein the cores are each simultaneously capable of decoding a different one of the LDPC code words,
- said at least one group includes a shared memory shared between the cores in the at least one group, and the shared memory stores a number (Nc) of predefined configurations,
- wherein each of the predefined configuration is associated with a parity matrix corresponding to an LDPC code, and the parity matrices associated with the predefined configurations are stored in the shared memory, and
- wherein each of the cores is adapted to be dynamically configured with any one of the predefined configurations stored in the shared memory to decode one of the LDPC code words using a respective one of the NC predefined combinations.
Dependencies are inferred from the claim text.