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US 12,542,567 B2Granted
Fast multi-payload-length error-correcting system and methods
AssigneeMicron Technology, Inc.
InventorsMarco Sforzin, Christophe Vincent Antoine Laurent
Life of this patent
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Abstract
Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.
Claims17
An error-correcting method comprising:
- receiving, at a processor circuit, an input;
- generating, at the processor circuit, a set of syndrome coefficients based on the input;
- generating, at the processor circuit, a parity vector for the input based on the set of syndrome coefficients by multiplying the set of syndrome coefficients by a mapping matrix, the mapping matrix providing a mapping between the set of syndrome coefficients and a syndrome vector;
- determining, at the processor circuit, a number of errors present in the input using the set of syndrome coefficients;
- and
- responsive to determining the number of errors present in the input, correcting, at the processor circuit, the number of errors using the parity vector to provide a corrected output.
3 more elements
An apparatus comprising:
- a first processor circuit, configured to:
- receive an input;
- generate a set of syndrome coefficients based on the input;
- generate a parity vector for the input based on the set of syndrome coefficients;
- determine a number of errors present in the input based on the set of syndrome coefficients;
- and
- responsive to determining the number of errors present in the input, correcting the number of errors using the parity vector to provide a corrected output;
- and
- a second processor circuit, configured to:
- generate a codeword, wherein the codeword is a codeword of a Bode-Chaudhuri-Hocquenghem (BCH) code;
- and
- transmit the codeword to the first processor circuit, wherein the input comprises a linear combination of the codeword and the number of errors.
9 more elements
A system comprising:
- a processing element configured to issue at least one of a read operation or a write operation;
- and
- a memory device comprising:
- a processor configured to:
- receive an input;
- generate a set of syndrome coefficients based on the input;
- generate a parity vector for the input based on the set of syndrome coefficients by multiplying the set of syndrome coefficients by a mapping matrix, the mapping matrix providing a mapping between the set of syndrome coefficients and a syndrome vector;
- determine a number of errors present in the input;
- and
- responsive to determining the number of errors present in the input, correcting the number of errors.
7 more elements
Dependencies are inferred from the claim text.