H03M 13/3966
Based on architectures providing a highly parallelized implementation
Official title: {based on architectures providing a highly parallelized implementation, e.g. based on systolic arrays}
H03M13/3966 (Based on architectures providing a highly parallelized implementation) appears on 7 US grants and 10 published applications in this corpus.
Search patents in H03M- Granted patents
- 7
- Published applications
- 10
- Assignees
- 8
- Inventors
- 27
- Latest grant
- 24 May 2016
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|---|---|---|
| 2002 | 0 | 1 |
| 2003 | 0 | 1 |
| 2004 | 0 | 1 |
| 2005 | 0 | 1 |
| 2006 | 0 | 1 |
| 2007 | 2 | 0 |
| 2008 | 0 | 0 |
| 2009 | 1 | 2 |
| 2010 | 1 | 0 |
| 2011 | 1 | 0 |
| 2012 | 0 | 0 |
| 2013 | 1 | 1 |
| 2014 | 0 | 1 |
| 2015 | 0 | 0 |
| 2016 | 1 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 1 |
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Recent patents
- Parallel implementation of maximum a posteriori probability decoder24 May 2016US 9,348,798 B2The MathWorks, Inc.
- Parallel implementation of maximum a posteriori probability decoder26 Nov 2013US 8,594,217 B2The MathWorks, Inc.
- Method of and apparatus for implementing fast orthogonal transforms of variable size11 Jan 2011US 7,870,176 B2ASOCS Ltd.
- Method of switching from parallel to serial MAP detector19 Jan 2010US 7,650,561 B1Seagate Technology LLC
- Method and system for a multi-channel add-compare-select unit3 Nov 2009US 7,613,990 B1Xilinx, Inc.
- Scl parallel decoding method and apparatus and device17 Jun 2021US 2021/0184701 A1
- Parallel implementation of maximum a posteriori probability decoder13 Feb 2014US 2014/0046995 A1The MathWorks, Inc.
- Parallel implementation of maximum a posteriori probability decoder6 Jun 2013US 2013/0142289 A1The MathWorks, Inc.
- Methods and Apparatuses for Parallel Decoding and Data Processing of Turbo Codes2 Jul 2009US 2009/0172495 A1VIA Telecom Co., Ltd.
- Low power viterbi decoder using scarce state transition and path pruning2 Apr 2009US 2009/0089648 A1The Hong Kong University of Science and Technology
Most cited
By later US patents
- Method of switching from parallel to serial MAP detector14US 7,650,561 B1Seagate Technology LLC · 2010
- Reduced-latency soft-in/soft-out module7US 7,197,691 B2University of Southern California · 2007
- Maximum likelihood detector and/or decoder7US 7,263,652 B2Arithmatica Limited · 2007
- Parallel implementation of maximum a posteriori probability decoder3US 8,594,217 B2The MathWorks, Inc. · 2013
- Method and system for a multi-channel add-compare-select unit2US 7,613,990 B1Xilinx, Inc. · 2009