Method of and apparatus for implementing fast orthogonal transforms of variable size
AssigneeASOCS Ltd.
InventorsDoron Solomon, Gilad Garon
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AssigneeASOCS Ltd.
InventorsDoron Solomon, Gilad Garon
Estimating the term…
A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture comprising: a computational unit configured and arranged so as to include one or more butterfly units; a block including one or more multipliers coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture; the storage unit including memory and multiplexing architecture; a multiplexer unit configured and arranged so as to time multiplex all of the butterfly computations of the transform using said computation unit for the one stage so that only one computation unit is required for the stage; and a controller configured and arranged so as to provide coefficients to the computational unit, and control the sizes of memory and multiplexing architecture in the storage unit; wherein the multipliers' coefficients, the coefficients of the computational unit, the sizes of memories, and multiplexing architecture, for each stage are modified as a function of the value of N. The architecture can be implemented as an integrated chip, and used in communication devices.
A reconfigurable architecture for performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being defined by N-points, wherein N can vary and the number of stages is a function of N, the architecture comprising:
An integrated chip comprising a reconfigurable architecture for performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being defined by N-points, wherein N can vary and the number of stages is a function of N, the architecture comprising:
A method of performing any one of a plurality of fast orthogonal transforms of vectors in multiple stages in accordance with any one of plurality of transform formats including fast Fourier transforms of different radixes and fast Walsh orthogonal transforms, including FFTs, inverse FFT transforms (IFFT), any sub-products including Discrete Cosine/Sine Transforms including DCT and DST, Walsh-Hadamard transforms, and any sub-product including CDMA DSSS Spreading/De-spreading, and any algorithm including a combination of two or more of the foregoing transforms, and other functionality including filtering by using concatenation of FFT and IFFT transforms, Hilbert transforms, predictions, interpolations and correlations, the size of a vector being defined by N-points, wherein N can vary and the number of stages is a function of N, the method comprising:
A method of performing a fast orthogonal transform of vectors in multiple stages in accordance with any one of a plurality of fast transform formats, including fast Fourier transforms of different radixes and fast Walsh orthogonal transforms, including FFTs, inverse FFT transforms (IFFT), any sub-products including Discrete Cosine/Sine Transforms including DCT and DST, Walsh-Hadamard transforms, and any sub-product including CDMA DSSS Spreading/De-spreading, and any algorithm including a combination of two or more of the foregoing transforms, and other functionality including filtering by using concatenation of FFT and IFFT transforms, Hilbert transforms, predictions, interpolations and correlations, the size of a vector being defined by N-points, wherein N can vary and the number of stages is a function of N, the method comprising:
A system of performing a fast orthogonal transform of vectors in multiple stages in accordance with any one of a plurality of fast transform formats, including fast Fourier transforms of different radixes and fast Walsh orthogonal transforms, including FFTs, inverse FFT transforms (IFFT), any sub-products including Discrete Cosine/Sine Transforms including DCT and DST, Walsh-Hadamard transforms, and any sub-product including CDMA DSSS Spreading/De-spreading, and any algorithm including a combination of two or more of the foregoing transforms, and other functionality including filtering by using concatenation of FFT and IFFT transforms, Hilbert transforms, predictions, interpolations and correlations, the size of a vector being defined by N-points, wherein N can vary and the number of stages is a function of N, the method comprising:
Dependencies are inferred from the claim text.