Low power viterbi decoder using scarce state transition and path pruning
AssigneeThe Hong Kong University of Science and Technology
InventorsChi Ying Tsui, Jie Jin
Life of this patent
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Abstract
Low power Viterbi decoder techniques using Scarce State Transition (SST) and path pruning and related methods and systems are provided, which facilitate practical implementations that reduce the computational overhead and power consumption. In addition, the invention provides uneven-partitioned memory architectures for the survivor memory unit that advantageously exploits the characteristic of the maximum likelihood state probability distribution of the SST decoder facilitating further power reduction. The disclosed details enable various refinements and modifications according to decoder and system design considerations.
Claims20
A method for low power signal decoding comprising:
- receiving a signal in a decoder, the decoder configured to perform a scarce state transition decoding algorithm and comprising a branch metric unit and a plurality of parallel add-compare-select units;
- determining a cumulative path metric of a zero state in the plurality of parallel add-compare-select units;
- calculating a branch metric with the branch metric unit based on the cumulative path metric;
- estimating a path metric for a path based on the branch metric according to the scarce state transition decoding algorithm;
- and
- pruning the path with the decoder based on a determination of the sign of the path metric.
A system for signal decoding comprising:
- an input component configured to receive a signal for decoding;
- a decoder component including a branch metric unit and a plurality of parallel add-compare-select units wherein the decoder component is configured to determine a cumulative path metric of a zero state, calculate a branch metric with the branch metric unit based on the cumulative path metric, and estimate a path metric for a path based on the branch metric;
- and
- pruning component configured to prune the path based on a determination of the sign of the path metric;
A low power decoding apparatus, comprising:
- a memory that retains instructions for determining a cumulative path metric of a zero state, for calculating a branch metric based on the cumulative path metric, for estimating a path metric for a path based on the branch metric, and for pruning the path based on a determination of the sign of the path metric;
- and
- a processor that is configured to execute the instructions within the memory.
Dependencies are inferred from the claim text.