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US 7,613,990 B1Granted
Method and system for a multi-channel add-compare-select unit
AssigneeXilinx, Inc.
InventorsWilliam A. Wilkie, David I. Lawrie, Elizabeth R. Cowie
Life of this patent
Estimating the term…
Abstract
A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.
Claims22
An add-compare-select circuit, comprising:
- an adder circuit to receive first and second sets of cost signals and configured to provide first and second summations of the first and second sets of cost signals;
- a first synchronization circuit, coupled to the adder circuit, the first synchronization circuit configured to store and provide the first and second summations in synchrony with a clock signal;
- a compare circuit to receive the first and second summations in response to the clock signal and configured to provide a comparison signal indicative of a relative difference between a magnitude of the first summation and a magnitude of the second summation;
- a second synchronization circuit, coupled to the first synchronization circuit and the compare circuit, the second synchronization circuit configured to store and provide the first and second summations in synchrony with the clock signal and to store and provide the comparison signal in synchrony with the clock signal;
- and
- a selection circuit, coupled to the second synchronization circuit, the selection circuit configured to provide a selected signal that is equal to one of the first or second summations in response to a value of the comparison signal.
3 more elements
An add-compare-select circuit, comprising:
- a first adder circuit to receive first and second sets of cost signals and configured to provide first and second summations of the first and second sets of cost signals;
- a first synchronization circuit, coupled to the adder circuit, the first synchronization circuit configured to store and provide the first and second summations in synchrony with a clock signal;
- a compare circuit to receive the first and second summations in response to the clock signal and configured to provide a first comparison signal indicative of a relative difference between a magnitude of the first summation and a magnitude of the second summation and further configured to provide a second comparison signal indicative of an actual difference between the magnitude of the first summation and the magnitude of the second summation;
- a memory device to receive the second comparison signal and configured to provide an offset signal in response to the second comparison signal;
- a selection circuit, coupled to the first synchronization circuit and the compare circuit, the selection circuit configured to provide a selected signal equal to one of the first or second summations in response to a value of the first comparison signal;
- and
- a second synchronization circuit, coupled to the selection circuit and the memory device, the second synchronization circuit configured to store and provide the selected and offset signals in synchrony with the clock signal.
4 more elements
An add-compare-select circuit, comprising:
- a first synchronization circuit to receive first and second sets of cost signals and a clock signal, the first synchronization circuit configured to store and provide the first and second sets of cost signals in synchrony with the clock signal;
- an adder circuit to receive the first and second sets of cost signals from the first synchronization circuit in response to the clock signal and configured to provide first and second summations of the first and second sets of cost signals;
- a second synchronization circuit, coupled to the adder circuit, the second synchronization circuit configured to store and provide the first and second summations in synchrony with the clock signal;
- a compare circuit to receive the first and second summations in response to the clock signal and configured to provide a comparison signal indicative of a relative difference between a magnitude of the first summation and a magnitude of the second summation;
- a third synchronization circuit, coupled to the second synchronization circuit and the compare circuit, the third synchronization circuit configured to store and provide the first and second summations in synchrony with the clock signal and to store and provide the comparison signal in synchrony with the clock signal;
- and
- a selection circuit, coupled to the third synchronization circuit, the selection circuit configured to provide a selected signal equal to one of the first or second summations in response to a value of the comparison signal.
4 more elements
Dependencies are inferred from the claim text.