G11C 7/1033

Using data registers of which only one stage is addressed for sequentially

Official title: {using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode}

G11C7/1033 (Using data registers of which only one stage is addressed for sequentially) appears on 105 US grants and 42 published applications in this corpus.

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Granted patents
105
Published applications
42
Assignees
48
Inventors
150
Latest grant
24 Mar 2026

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G11C 7/1033: granted patents and published applications per publication year
YearGranted patentsPublished applications
198210
198310
198420
198510
198630
198720
198830
198970
199020
199100
199220
199340
199450
199510
199640
199750
199880
199940
200020
200130
200224
200311
200442
200512
200621
200712
200822
200910
201013
201121
201230
201303
201431
201534
201616
201761
201820
201911
202022
202112
202211
202321
202411
202501
202620

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