Memory device for outputting data and method of operating the same
AssigneeSK hynix Inc.
InventorSu Han Lee
Life of this patent
Estimating the term…
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AssigneeSK hynix Inc.
InventorSu Han Lee
Estimating the term…
A memory device for outputting data, and a method of operating the same, includes a cache latch group including a plurality of cache latches that are sequentially arranged, wherein a plurality of odd cache latches and a plurality of even cache latches that are included in the plurality of cache latches are alternately arranged. The memory device also includes a sense amplifier configured to be coupled to the plurality of odd cache latches through a first bit output line group and coupled to the plurality of even cache latches through a second bit output line group, alternately. The memory device additionally includes a bit output line selection circuit configured to alternately couple the sense amplifier to the first bit output line group and the second bit output line group in response to a bit output line selection signal.
A memory device, comprising:
A memory device, comprising:
A method of operating a memory device, comprising:
Dependencies are inferred from the claim text.