Method and structure for performing pipeline burst accesses in a semiconductor memory

A memory system comprises:

• a memory array having a memory cycle time and an input/output (I/O) cycle time, wherein the memory cycle time is longer than the I/O cycle time;
• and
• a pipeline-burst access circuit coupled to the memory array, wherein the pipeline-burst access circuit enables pipeline-burst read operations or pipeline-burst write operations to be performed with the same access latency across the entire address range of the memory array;
• wherein the pipeline-burst access circuit comprises a write buffer coupled to the memory array, wherein the write buffer stores a set of data values for an entire burst write sequence;
• wherein the write buffer is controlled to transfer a plurality of data values to the memory array simultaneously.

A memory system comprising:

• a dynamic random access memory (DRAM);
• and
• a memory control sequencer for accessing the DRAM, wherein the memory control sequencer generates a row access signal and a column access signal for controlling the memory operations of the DRAM in response to a single external access signal and a clock signal;
• wherein the memory control sequencer comprises circuitry for detecting the reception of the external access signal during a first cycle of the clock signal, asserting the row access signal during the first cycle and a consecutive second cycle of the clock signal, asserting the column access signal during the second cycle of the clock signal, de-asserting the row and column access signals during a consecutive third cycle of the clock signal, and precharging the DRAM during the third cycle of the clock signal.

A memory system comprises:

• a dynamic random access memory (DRAM);
• and
• a memory control sequencer for accessing the DRAM wherein, the memory control sequencer generates, a row access signal and a column access signal for controlling the memory operations of the DRAM in response to an external access signal and a clock signal;
• wherein the memory control sequencer comprises circuitry for blocking the external access signal for three clock cycles upon detecting the external access signal.

A method of operating a memory array having a memory cycle time and an input/output (I/O) cycle time, wherein the memory cycle time is longer than the I/O cycle time, the method comprising the steps of:

• initiating a read access to the memory array during a first clock cycle;
• reading a first set of data values from the memory array during a second clock cycle;
• storing the first set of data values read from the memory array in a first data storage circuit during the second clock cycle;
• storing the first set of data values in a second data storage circuit during the second clock cycle, wherein the second data storage circuit is cascaded with the first data storage circuit;
• and then
• isolating the second data storage circuit from the first data storage circuit during a third clock cycle.

A method of operating a memory array having a memory cycle time and an input/output (I/O) cycle time, wherein the memory cycle time is longer than the I/O cycle time, the method comprising the steps of:

• storing a first set of data values in a first data storage circuit during a first write transaction;
• storing a first address corresponding to the first set of data values in a first address storage circuit during the first write transaction;
• shifting the first set of data values from the first data storage circuit to a second data storage circuit during the first write transaction;
• shifting the first address from the first address storage circuit to a second address storage circuit during the first write transaction;
• providing the first set of data values and the first address to the memory array during a second write transaction, whereby the first set of data values are written to the memory array during a single clock cycle;
• storing a second set of data values in the first data storage circuit during the second write transaction;
• storing a second address corresponding to the second set of data values in the first address storage circuit during the second write transaction;
• shifting the second set of data values from the first data storage circuit to a second data storage circuit after the first set of data values has been provided to the memory array;
• and
• shifting the second address from the first address storage circuit to a second address storage circuit after the first address has been provided to the memory array.