G11C 2229/746
Before packaging
G11C2229/746 (Before packaging) appears on 4 US grants and 4 published applications in this corpus.
Search patents in G11C- Granted patents
- 4
- Published applications
- 4
- Assignees
- 3
- Inventors
- 11
- Latest grant
- 23 Aug 2016
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2005 | 0 | 1 |
| 2006 | 0 | 1 |
| 2007 | 1 | 0 |
| 2008 | 1 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 1 |
| 2014 | 1 | 1 |
| 2015 | 0 | 0 |
| 2016 | 1 | 0 |
By publication year.
Recent patents
- Semiconductor package including stacked chips and method of fabricating the same23 Aug 2016US 9,424,954 B2Samsung Electronics Co., Ltd.
- Semiconductor memory device and defective cell relieving method16 Sep 2014US 8,837,240 B2Kabushiki Kaisha Toshiba
- Memory circuit comprising redundant memory areas13 May 2008US 7,373,562 B2Infineon Technologies AG
- Semiconductor memory device with test circuit28 Aug 2007US 7,263,010 B2Kabushiki Kaisha Toshiba
- Semiconductor package including stacked chips and method of fabricating the same27 Nov 2014US 2014/0347943 A1Samsung Electronics Co., Ltd.
- Semiconductor memory device and defective cell relieving method28 Mar 2013US 2013/0077420 A1Kabushiki Kaisha Toshiba
- Semiconductor memory device5 Oct 2006US 2006/0221729 A1Kabushiki Kaisha Toshiba
- Memory circuit comprising redundant memory areas22 Dec 2005US 2005/0281076 A1Infineon Technologies AG
Most cited
By later US patents
- Memory circuit comprising redundant memory areas9US 7,373,562 B2Infineon Technologies AG · 2008
- Semiconductor memory device with test circuit7US 7,263,010 B2Kabushiki Kaisha Toshiba · 2007
- Semiconductor package including stacked chips and method of fabricating the same2US 9,424,954 B2Samsung Electronics Co., Ltd. · 2016