Semiconductor memory device and defective cell relieving method

A semiconductor device, comprising:

• a first semiconductor chip including a semiconductor memory device and provided in a package;
• a second semiconductor chip including a control circuit configured to control the semiconductor memory device and provided in the package;
• the first semiconductor chip including:
• a memory cell array including a normal cell array configured by arranging memory cells at intersections of a plurality of first lines and a plurality of second lines, and a spare cell array configured by arranging spare cells for replacing the normal cell array;
• a first defect address data storage circuit configured to store first defect address data indicating an address of a defective memory cell in the memory cell array;
• a first comparison circuit configured to compare address data indicating an address of a memory cell with the first defect address data to output a first match signal in case of matching;
• and
• a decoder configured to decode the address data to select the memory cell in the normal cell array, or, when the first match signal is output, to select a first spare cell in the spare cell array instead of the memory cell in the normal cell array,
• the second semiconductor chip including:
• a control circuit configured to control an operation of the first semiconductor chip;
• a second defect address data storage circuit configured to store second defect address data indicating an address of a defective memory cell in the memory cell array;
• and
• a second comparison circuit configured to compare the address data with the second defect address data to output a second match signal in case of matching, and
• the decoder being configured to select a second spare cell in the spare cell array when the second match signal is output,
• wherein the first semiconductor chip includes a normal bank and a spare bank,
• the normal bank includes the normal cell array and a first spare cell array, and
• the spare bank includes the normal cell array and a second spare cell array.