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US 7,373,562 B2Granted
Memory circuit comprising redundant memory areas
AssigneeInfineon Technologies AG
InventorPeter Poechmueller
Life of this patent
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Abstract
The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the redundant memory areas, each redundancy circuit having permanently settable storage elements in order, in a first setting state, to address the assigned redundant memory area in the event of addressing of the regular memory area with a memory address determined by the first setting state, each redundancy circuit, in a second setting state, addressing the assigned redundant memory area in a manner dependent on an activation signal.
Claims21
A memory device, comprising:
- a plurality of regular memory areas;
- a plurality of redundant memory areas;
- a plurality of redundancy circuits, each having a plurality of first settable elements and configured to activate a corresponding redundant memory area to replace a failing regular memory area in response to,
- a) detecting an address for the failing regular memory area stored in the first settable elements when a second settable element is in a first state, or
- b) an activation signal when the second settable element is in a second state;
- and
- an error correction circuit having a plurality of third settable elements and configured to, in response to detecting an address for a failing regular memory area stored in the third settable elements, generate the activation signal to cause one of the plurality of redundancy circuits whose second settable element is in the second state to activate a corresponding redundant memory area.
4 more elements
A memory device, comprising:
- a plurality of regular memory areas;
- a plurality of redundant memory areas;
- a plurality of redundancy circuits configured to activate a corresponding redundant memory area to replace a failing regular memory area in response to,
- a) detecting the presence of an address for the failing regular memory area previously stored in first storage elements, or
- b) detecting the presence of an activation signal supplied by an error correction circuit;
- and
- the error correction circuit having second storage elements and configured to, in response to detecting an address for a failing regular memory area stored in the second storage elements, generate the activation signal to cause one of the plurality of redundancy circuits to activate a corresponding redundant memory area.
4 more elements
A system, comprising:
- a memory device, comprising a plurality of regular memory areas, a plurality of redundant memory areas, and a plurality of redundancy circuits, each having a plurality of laser fuses and configured to activate a corresponding redundant memory area to replace a failing regular memory area in response to detecting an address for the failing regular memory area stored in the laser fuses when a second fuse in a first state, or an activation signal when the second fuse is in a second state;
- and
- an error correction circuit having a plurality of electrically programmable fuses and configured to, in response to detecting an address for a failing regular memory area stored in the electrically programmable fuses, generate the activation signal to cause one of the plurality of redundancy circuits whose second fuse is in the second state to activate a corresponding redundant memory area.
A method for replacing failing regular memory areas of a memory device with redundant memory areas, comprising:
- identifying a failing regular memory area;
- storing an address for the failing regular memory area in first settable memory elements of an error correction circuit configured to generate an activation signal in response to detecting the address stored in the first settable memory elements of the error correction circuit;
- and
- altering a state of a second settable memory element of a redundancy circuit to a first state, wherein the redundancy circuit is configured to activate a corresponding redundant memory area to replace a failing regular memory area in response to:
- a) a first signal when the second settable memory element of the redundancy circuit is in the first state, wherein the first signal is the activation signal, and
- b) detecting an address for the failing regular memory area stored in third settable elements of the redundancy circuit when the second settable element is in a second state.
3 more elements
A method for replacing failing regular memory areas of a memory device with redundant memory areas, comprising:
- during a first test,
- identifying a failing regular memory area, and
- selecting a redundancy circuit for replacing the failing memory area by storing the address of the failing regular memory area in first settable memory elements of the redundancy circuit, where the redundancy circuit activates a corresponding redundant memory area in response to an access to the failing regular memory area;
- and
- during a second test,
- identifying another failing regular memory area,
- storing an address for the other failing regular memory area in settable memory elements of an error correction circuit, where the error correction circuit generates an activation signal in response to an access to the other failing regular memory area, and
- altering a state of a settable memory element of another redundancy circuit for replacing a failing memory area, where the other redundancy circuit activates a corresponding redundant memory area in response to the activation signal generated by the error correction circuit.
5 more elements
A memory device, comprising:
- a plurality of regular memory areas;
- a plurality of redundant memory areas;
- a plurality of redundancy circuits configured to activate a corresponding redundant memory area to replace a failing regular memory area in response to,
- a) detecting an address for the failing regular memory area stored in the first settable elements when a second settable element is in a first state, or
- b) an activation signal when the second settable element is in a second state;
- and
- an error correction circuit configured to generate the activation signal, in response to detecting an address for a failing regular memory area stored in the third settable elements, to cause one of the plurality of redundancy circuits whose second settable element is in the second state to activate a corresponding redundant memory area.
4 more elements
Dependencies are inferred from the claim text.