G06F 9/3812
With instruction modification
Official title: {with instruction modification, e.g. store into instruction stream}
G06F9/3812 (With instruction modification) appears on 216 US grants and 96 published applications in this corpus.
Search patents in G06F- Granted patents
- 216
- Published applications
- 96
- Assignees
- 54
- Inventors
- 345
- Latest grant
- 7 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 2 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 3 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 3 | 0 |
| 1994 | 2 | 0 |
| 1995 | 7 | 0 |
| 1996 | 8 | 0 |
| 1997 | 15 | 0 |
| 1998 | 30 | 0 |
| 1999 | 15 | 0 |
| 2000 | 9 | 0 |
| 2001 | 6 | 2 |
| 2002 | 10 | 1 |
| 2003 | 7 | 5 |
| 2004 | 2 | 5 |
| 2005 | 3 | 0 |
| 2006 | 2 | 3 |
| 2007 | 3 | 6 |
| 2008 | 4 | 4 |
| 2009 | 4 | 2 |
| 2010 | 7 | 4 |
| 2011 | 11 | 3 |
| 2012 | 4 | 5 |
| 2013 | 5 | 7 |
| 2014 | 3 | 3 |
| 2015 | 3 | 1 |
| 2016 | 5 | 3 |
| 2017 | 2 | 6 |
| 2018 | 1 | 5 |
| 2019 | 8 | 3 |
| 2020 | 3 | 2 |
| 2021 | 7 | 10 |
| 2022 | 6 | 4 |
| 2023 | 2 | 5 |
| 2024 | 4 | 1 |
| 2025 | 5 | 3 |
| 2026 | 1 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Data pipeline controller7 Jul 2026US 12,675,498 B2AT&T Intellectual Property I, L. P.
- Apparatus and method23 Sep 2025US 12,423,107 B2Arm Limited
- Systems and methods for optimizing authentication branch instructions23 Sep 2025US 12,423,408 B1Apple Inc.
- Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm6 May 2025US 12,293,188 B2Cornami, Inc.
- Methods and apparatus for context switching29 Apr 2025US 12,288,091 B2Arm Limited
- Atomic compare and swap using micro-operations5 Mar 2026US 2026/0064421 A1Akeana, Inc.
- Method and Apparatus for Configuring a Reduced Instruction Set Computer Processor Architecture to Execute a Fully Homomorphic Encryption Algorithm12 Feb 2026US 2026/0044347 A1
- Systems and Methods to Provide Instructions to Coprocessors15 Jan 2026US 2026/0017058 A1
- Systems and Methods for Optimizing Authentication Branch Instructions11 Dec 2025US 2025/0378157 A1Apple Inc.
- Apparatus and method21 Aug 2025US 2025/0265086 A1Arm Limited
Most cited
By later US patents
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency285US 5,226,130 ANexgen Microsystems · 1993
- Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer215US 5,721,855 AIntel Corporation · 1998
- Combining hardware and software to provide an improved microprocessor192US 6,031,992 ATransmeta Corporation · 2000
- Method and apparatus for debugging an integrated circuit172US 6,499,123 B1Advanced Micro Devices, Inc. · 2002