G06F 9/30196
Using decoder
Official title: {using decoder, e.g. decoder per instruction set, adaptable or programmable decoders}
G06F9/30196 (Using decoder) appears on 340 US grants and 317 published applications in this corpus.
Search patents in G06F- Granted patents
- 340
- Published applications
- 317
- Assignees
- 117
- Inventors
- 598
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 2 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 2 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 3 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 3 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 2 | 0 |
| 1996 | 4 | 0 |
| 1997 | 4 | 0 |
| 1998 | 11 | 0 |
| 1999 | 7 | 0 |
| 2000 | 17 | 0 |
| 2001 | 5 | 2 |
| 2002 | 3 | 4 |
| 2003 | 3 | 6 |
| 2004 | 4 | 11 |
| 2005 | 3 | 3 |
| 2006 | 6 | 8 |
| 2007 | 4 | 7 |
| 2008 | 4 | 2 |
| 2009 | 6 | 9 |
| 2010 | 5 | 4 |
| 2011 | 6 | 6 |
| 2012 | 6 | 6 |
| 2013 | 3 | 20 |
| 2014 | 7 | 7 |
| 2015 | 10 | 13 |
| 2016 | 18 | 13 |
| 2017 | 16 | 16 |
| 2018 | 10 | 8 |
| 2019 | 15 | 33 |
| 2020 | 21 | 35 |
| 2021 | 35 | 30 |
| 2022 | 28 | 26 |
| 2023 | 22 | 14 |
| 2024 | 19 | 18 |
| 2025 | 12 | 13 |
| 2026 | 9 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Processing-in-memory device having a plurality of global buffers and processing-in-memory system including the same8 Sep 2026US 12,730,632 B2SK hynix Inc.
- System and method enabling one-hot neural networks on a machine learning compute platform8 Sep 2026US 12,730,643 B2Intel Corporation
- Systems, methods, and apparatuses for tile transpose9 Jun 2026US 12,650,839 B2Intel Corporation
- Shared prefetch instruction and support2 Jun 2026US 12,645,454 B2Intel Corporation
- Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor5 May 2026US 12,619,463 B2Micron Technology, Inc.
- Systems, methods, and apparatuses for tile transpose24 Sep 2026US 2026/0288459 A1Intel Products IP LLC
- Container-based instruction set30 Jul 2026US 2026/0219890 A1Arm Limited
- Safety supervised general purpose computing devices4 Jun 2026US 2026/0154073 A1Traxen Inc.
- Modular pipelines for accessing digital data9 Oct 2025US 2025/0315265 A1Bevara Technologies, LLC
- Instruction operand prefixing combinator and decoder for extensibility and backward compatibility2 Oct 2025US 2025/0306938 A1
Most cited
By later US patents
- Dual-architecture super-scalar pipeline285US 5,598,546 AExponential Technology, Inc. · 1997
- Multiple tokenization for authentication283US 9,280,765 B2Visa International Service Association · 2016
- Computer for execution of RISC and CISC instruction sets222US 7,047,394 B1ATI International SRL · 2006
- Method for compiling and executing programs for reprogrammable instruction set accelerator218US 5,752,035 AXilinx, Inc. · 1998
- Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures215US 5,854,913 AInternational Business Machines Corporation · 1998