Shared prefetch instruction and support

A method comprising:

• decoding a single instruction, the single instruction having at least one field for an opcode, at least one field for a source operand to provide a memory address for at least a byte of data, wherein the opcode is to indicate that circuitry is to fetch of a line of data from memory at the provided address that contains the byte specified by the source operand and store that byte in a cache local to a requester and in a last level cache, wherein the byte of data is to be stored in a shared state in both the cache local to the requester and in the last level cache;
• and
• executing the decoded instruction according to the opcode.

A non-transitory machine-readable medium having stored thereon at least an instance of a single instruction which when processed by a machine is to cause the machine to perform a method comprising:

• decoding the instance of the single instruction, the instance of the single instruction having at least one field for an opcode, at least one field for a source operand to provide a memory address for at least a byte of data, wherein the opcode is to indicate that circuitry is to fetch of a line of data from memory at the provided address that contains the byte specified by the source operand and store that byte in a cache local to a requester and in a last level cache, wherein the byte of data is to be stored in a shared state in both the cache local to the requester and in the last level cache;
• and
• executing the decoded instruction according to the opcode.