Method for compiling and executing programs for reprogrammable instruction set accelerator
AssigneeXilinx, Inc.
InventorStephen M. Trimberger
Life of this patent
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AssigneeXilinx, Inc.
InventorStephen M. Trimberger
Estimating the term…
A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a set of program instructions, to provide an on chip reprogrammable instruction set accelerator RISA. Reprogrammable execution units may be made using field programmable gate array technology having configuration stores. Techniques for translating a computer program into executable code relying on the RISA involve providing a library of defined and programmed instructions, and compiling a program using the library to produce an executable version of the program using both defined and programmed instructions. The executable version can be optimized to conserve configuration resources for the programmable execution unit, or to optimize speed of execution. Thus, seldom used programmed instructions in the final object code can be replaced with segments of defined instructions to conserve configuration resources. Alternatively, specially prepared sets of programmed instructions can be used to compile programs. A variety of versions are formed using separate sets of programmed instructions and the best final version is selected. In addition, commonly used segments of instructions can be synthesized into a programmed instruction dynamically.
A method for translating a computer program to executable code, comprising:
A method for translating a computer program to executable code, comprising:
A method for executing a computer program including a particular function, comprising:
A method for executing a computer program comprising:
Dependencies are inferred from the claim text.