G06F 9/30094
Condition code generation
Official title: {Condition code generation, e.g. Carry, Zero flag}
G06F9/30094 (Condition code generation) appears on 764 US grants and 538 published applications in this corpus.
Search patents in G06F- Granted patents
- 764
- Published applications
- 538
- Assignees
- 173
- Inventors
- 1,225
- Latest grant
- 28 Jul 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 2 | 0 |
| 1981 | 2 | 0 |
| 1982 | 3 | 0 |
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 4 | 0 |
| 1987 | 2 | 0 |
| 1988 | 4 | 0 |
| 1989 | 4 | 0 |
| 1990 | 6 | 0 |
| 1991 | 3 | 0 |
| 1992 | 5 | 0 |
| 1993 | 14 | 0 |
| 1994 | 9 | 0 |
| 1995 | 10 | 0 |
| 1996 | 26 | 0 |
| 1997 | 33 | 0 |
| 1998 | 49 | 0 |
| 1999 | 29 | 0 |
| 2000 | 28 | 0 |
| 2001 | 36 | 5 |
| 2002 | 18 | 24 |
| 2003 | 24 | 25 |
| 2004 | 11 | 32 |
| 2005 | 18 | 17 |
| 2006 | 23 | 16 |
| 2007 | 24 | 18 |
| 2008 | 14 | 38 |
| 2009 | 14 | 17 |
| 2010 | 21 | 15 |
| 2011 | 18 | 17 |
| 2012 | 16 | 19 |
| 2013 | 17 | 54 |
| 2014 | 31 | 21 |
| 2015 | 43 | 18 |
| 2016 | 22 | 22 |
| 2017 | 19 | 23 |
| 2018 | 21 | 28 |
| 2019 | 30 | 25 |
| 2020 | 25 | 21 |
| 2021 | 22 | 22 |
| 2022 | 17 | 14 |
| 2023 | 19 | 13 |
| 2024 | 13 | 14 |
| 2025 | 9 | 9 |
| 2026 | 3 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Convert instruction with overflow result control28 Jul 2026US 12,693,859 B2International Business Machines Corporation
- Fused instruction operation for performing an operation and adjusting a sign of the operation result19 May 2026US 12,632,258 B1Apple Inc.
- Pipeline for processing transactions27 Jan 2026US 12,536,032 B2Capital One Services, LLC
- Fast carry-calculation oriented redundancy-tolerated fixed-point number coding for massive parallel ALU circuitry design in GPU, TPU, NPU, AI infer chip, CPU, and other computing devices30 Dec 2025US 12,511,123 B2
- Register file structures combining vector and scalar data with global and local accesses16 Dec 2025US 12,498,925 B2Texas Instruments Incorporated
- 8-bit floating point comparison instructions1 Oct 2026US 2026/0299944 A1Intel Products IP LLC
- Information processing method, information processing architecture, and program10 Sep 2026US 2026/0267640 A1The University of Tokyo
- Preventing performance of conditional instructions9 Jul 2026US 2026/0195131 A1NVIDIA Corporation
- Enabling performance of conditional instructions9 Jul 2026US 2026/0195139 A1NVIDIA Corporation
- Broadcast translation lookaside buffer invalidation2 Jul 2026US 2026/0186784 A1
Most cited
By later US patents
- Packet processing system including a policy engine having a classification unit624US 6,157,955 AIntel Corporation · 2000
- System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling448US 5,179,702 ASupercomputer Systems Limited Partnership · 1993
- Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes323US 6,195,676 B1Silicon Graphics, Inc. · 2001
- High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations320US 5,651,125 AAdvanced Micro Devices, Inc. · 1997
- Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode317US 5,239,654 ATexas Instruments Incorporated · 1993