Fused instruction operation for performing an operation and adjusting a sign of the operation result

A method, comprising:

• detecting, by a hardware fetch and decode circuit of a processor, a first instruction that is executable by the processor to perform an arithmetic/logic operation and a second instruction that is executable by the processor to adjust a sign of a result of the arithmetic/logic operation;
• decoding, by the hardware fetch and decode circuit, the first instruction and the second instruction into a first instruction operation and a second instruction operation for execution;
• determining, by the hardware fetch and decode circuit, that the first instruction and the second instruction are eligible for fusion;
• in response to determining that the first instruction and the second instruction are eligible for fusion, generating for the first instruction operation an indicator of eligibility for fusion with the second instruction operation;
• forwarding, to a hardware map-dispatch-rename (MDR) circuit of the processor, the first instruction operation, the indicator of eligibility and the second instruction operation;
• based in part on the indicator of eligibility, determining, in the hardware MDR circuit, that the first instruction operation and the second instruction operation should be fused;
• in response to determining that the first instruction operation and the second instruction operation should be fused, fusing the first instruction operation and the second instruction operation into a fused instruction operation that is executable by the processor to perform the arithmetic/logic operation and adjust the sign of the result;
• and
• executing, by the processor, the fused instruction operation.

A system, comprising:

• one or more memory controllers;
• one or more peripheral components;
• a processor;
• and
• a communication fabric configured to interconnect the one or more memory controllers, the one or more peripheral components and the processor, wherein the processor includes:
• a hardware fetch and decode circuit including hardware pair detector circuitry, wherein the hardware pair detector circuitry is configured to:
• receive fetched instructions;
• detect a first instruction that is executable to perform an arithmetic/logic operation and a second instruction that is executable to adjust a sign of a result of the arithmetic/logic operation;
• determine whether the first instruction and the second instruction are eligible for fusion;
• and
• in response to determining that the first instruction and the second instruction are eligible for fusion,
• generate, for a first instruction operation decoded from the first instruction, an indicator of eligibility for fusion with a second instruction operation decoded from the second instruction;
• and
• forward from the hardware fetch and decode circuit the first instruction operation with the indicator of eligibility and the second instruction operation;
• a hardware map-dispatch-rename (MDR) circuit including hardware fusion circuitry, wherein:
• the hardware MDR circuit is configured to:
• receive the first instruction operation and the second instruction operation;
• detect the indicator of eligibility, if received;
• and
• based on whether the indicator of eligibility is detected, determine whether to fuse the first instruction operation and the second instruction operation;
• and
• the hardware fusion circuitry is configured to fuse the first instruction operation and the second instruction operation into a fused instruction operation that is executable to perform the arithmetic/logic operation and adjust the sign of the result;
• and
• hardware execution circuitry coupled to the hardware fusion circuitry and configured to execute the fused instruction operation.