G06F 7/605
Additive or subtractive mixing of two pulse rates into one
Official title: {Additive or subtractive mixing of two pulse rates into one (beat-frequency oscillators H03B21/00; input circuits of electric counters, e.g. up-down counters H03K21/00)}
G06F7/605 (Additive or subtractive mixing of two pulse rates into one) appears on 16 US grants and 12 published applications in this corpus.
Search patents in G06F- Granted patents
- 16
- Published applications
- 12
- Assignees
- 12
- Inventors
- 19
- Latest grant
- 26 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 1 | 0 |
| 1998 | 2 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 1 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 1 | 0 |
| 2013 | 0 | 1 |
| 2014 | 0 | 0 |
| 2015 | 1 | 1 |
| 2016 | 1 | 0 |
| 2017 | 1 | 1 |
| 2018 | 1 | 2 |
| 2019 | 1 | 1 |
| 2020 | 1 | 2 |
| 2021 | 2 | 0 |
| 2022 | 1 | 1 |
| 2023 | 0 | 0 |
| 2024 | 0 | 0 |
| 2025 | 0 | 1 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
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Most cited
By later US patents
- Software reconfigurable digital phase lock loop architecture23US 8,321,489 B2National Semiconductor Corporation · 2012
- Phase locked loop having voltage controlled oscillator utilizing combinational logic22US 5,614,868 AVLSI Technology, Inc. · 1997
- Phase locked loop circuitry including a multiple frequency output voltage controlled oscillator circuit15US 5,786,732 AVLSI Technology, Inc. · 1998
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