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US 10,936,286 B2Granted
FPGA logic cell with improved support for counters
AssigneeMicrosemi SoC Corporation
InventorsJonathan W. Greene, Joel Landry
Life of this patent
Estimating the term…
Abstract
A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.
Claims5
A logic cell for a programmable logic integrated circuit comprising:
- K data inputs;
- a primary output;
- a carry-in input;
- a carry-out output;
- a counter input;
- a sum output;
- a K-input lookup table (LUT) having K LUT inputs each connected to a different one of the K data inputs, and a LUT output directly connected to the primary output, the K-input LUT including:
- a first (K-1)-input lookup table LUT and a second (K-1)-input LUT both sharing in common second through Kth inputs to the K-input LUT, each of the first and second (K-1)-input LUTs having an output;
- a first multiplexer having a first input coupled to the output of the first (K-1)-input LUT, a second data input coupled to the output of the second (K-1)-input LUT, and a select input coupled to a first input of the K-input LUT, the first multiplexer having an output forming the LUT output that is directly connected to the primary output;
- and
- a carry circuit comprising:
- a second multiplexer having a first data input coupled to the output of one of the first and second (K-1)-input LUTs, a second data input coupled to a logic-low constant voltage, select inputs coupled to configuration circuitry for the logic cell, and a data output;
- a third multiplexer having a first data input coupled to the counter input of the logic cell, a second data input coupled to the LUT output, a third data input coupled to a logic-low constant voltage, select inputs coupled to configuration circuitry for the logic cell, and a data output;
- a carry-out multiplexer having a first data input coupled to the data output of the second multiplexer, a second data input coupled to the carry-in input of the logic cell, a select input coupled to the data output of the third multiplexer, and a data output coupled to the carry-out output of the logic cell;
- and
- an exclusive-OR gate having a first input coupled to the carry-in input of the logic cell, a second input coupled to the data output of the third multiplexer, and an output coupled to the sum output of the logic cell.
13 more elements
A logic cell for a programmable logic integrated circuit comprising:
- a first data input and a plurality of additional data inputs;
- a first lookup table (LUT) having an output and a plurality of inputs, each of the plurality of inputs of the first LUT connected to a respective one of the plurality of additional data inputs;
- a second LUT having an output and a plurality of inputs, each of the plurality of inputs of the second LUT connected to a respective one of the plurality of additional data inputs;
- a first multiplexer having a first input coupled to the output of the first LUT, a second input coupled to the output of the second LUT, and a select input coupled to the first data input, the first multiplexer having an output that is directly connected to a primary output of the logic cell;
- a second multiplexer having a first data input coupled to the output of the second LUT, a second data input coupled to a logic-low constant voltage, select inputs coupled to configuration circuitry for the logic cell and a data output;
- a third multiplexer having a first data input coupled to a counter input of the logic cell, a second data input coupled to the primary output of the logic cell, a third data input coupled to a logic-low constant voltage, select inputs coupled to configuration circuitry for the logic cell and a data output;
- a carry-out multiplexer having a first data input coupled to the data output of the second multiplexer, a second data input coupled to a carry-in input of the logic cell, a select input coupled to the data output of the third multiplexer and a data output coupled to a carry-out output of the logic cell;
- and
- an exclusive-OR gate having a first input coupled to the carry-in input of the logic cell, a second input coupled to the data output of the third multiplexer, and an output coupled to a sum output of the logic cell.
6 more elements
Dependencies are inferred from the claim text.