Software reconfigurable digital phase lock loop architecture
AssigneeNational Semiconductor Corporation
InventorsRoman Staszewski, Robert B. Staszewski, Fuqiang Shi
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Abstract
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
Claims17
A processor based phase locked loop (PLL), comprising:
- an oscillator operative to generate a radio frequency (RF) signal having a frequency determined in accordance with a tuning command input thereto;
- a processor operative to generate said tuning command, said processor comprising:
- a reconfigurable calculation unit (RCU) operative to perform atomic operations required to implement said phase locked loop;
- data memory coupled to said reconfigurable calculation unit for storing phase locked loop state information;
- program memory coupled to said reconfigurable calculation unit for storing a plurality of instructions that when executed on said processor implement said phase locked loop;
- and
- said processor having an instruction set, wherein each instruction is operative to perform an atomic operation of said phase locked loop.
A radio, comprising:
- a transmitter coupled to an antenna, said transmitter comprising a software based phase locked loop (PLL), said phase locked loop comprising:
- an oscillator operative to generate a radio frequency (RF) signal having a frequency determined in accordance with a tuning command input thereto;
- a processor operative to generate said tuning command, said processor comprising:
- a reconfigurable calculation unit (RCU) operative to perform atomic operations required to implement said phase locked loop;
- data memory coupled to said reconfigurable calculation unit for storing phase locked loop state information;
- program memory coupled to said reconfigurable calculation unit for storing a plurality of instructions that when executed on said processor implement said phase locked loop;
- said processor having an instruction set, wherein each instruction is operative to perform an atomic operation of said phase locked loop;
- a receiver coupled to said antenna;
- and
- a baseband processor coupled to said transmitter and said receiver.
Dependencies are inferred from the claim text.