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US 2020/0150925 A1Published application
Fpga logic cell with improved support for counters
AssigneeMicrosemi SoC Corporation
InventorsJonathan W. Greene, Joel Landry
Life of this patent
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Abstract
A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.
Claims20
A logic cell for a programmable logic integrated circuit wherein:
- K is the largest number such that the logic cell can compute any function of K inputs;
- and
- the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 inputs.
A logic cell for a programmable logic integrated circuit wherein:
- the logic cell has only 4 inputs connected to a programmable routing network;
- the logic cell has only two outputs connected to the programmable routing network;
- the logic cell has a carry-in input;
- the logic cell may be configured in a first way such that the value of the carry-in input appears at one of the outputs, and in parallel any function of the 4 inputs appears at the other output;
- and
- the logic cell may be configured in a second way to implement one bit of a two-input adder, with the sum bit appearing at one of the two outputs.
3 more elements
A logic cell for a programmable logic integrated circuit comprising:
- a carry input;
- a 2-input carry-out multiplexer producing a carry-out signal;
- a 2-input exclusive-OR gate having a first input driven by the carry input and a second input driven by a signal that does not also drive the programmable routing network;
- a multiplexer producing a signal P that drives a select input of the carry out multiplexer and one input of the exclusive-OR gate.
1 more element
A logic cell for a programmable logic integrated circuit comprising:
- K data inputs;
- a primary output;
- a carry-in input;
- a carry-out output;
- a counter input;
- a sum output;
- a K-input lookup table (LUT) having K LUT inputs each connected to a different one of the K data inputs, and a LUT output directly connected to the primary output, the K-input LUT including:
- a first (K-1)-input lookup table LUT and a second (K-1)-input LUT both sharing in common second through Kth inputs to the K-input LUT, each of the first and second (K-1)-input LUTs having an output;
- a first multiplexer having a first input coupled to the output of the first (K-1)-input LUT, a second data input coupled to the output of the second (K-1)-input LUT, and a select input coupled to a first input of the K-input LUT, the first multiplexer having an output forming the LUT output that is directly connected to the primary output;
- and
- a carry circuit.
8 more elements
Dependencies are inferred from the claim text.