Phase locked loop circuitry including a multiple frequency output voltage controlled oscillator circuit

Abstract

A phase locked loop including a comparator, a VCO controller, and a VCO having a multi-stage oscillator portion and a combinational logic portion. The comparator is responsive to an input clock and a VCO comparison clock and is operative to produce a comparator output signal. The VCO controller is responsive to the comparator output signal and is operative to produce a VCO control signal. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of the VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency. A method for multiplying an input clock frequency includes the steps of applying an input clock to a delay chain, developing a plurality of phase-shifted clocks by tapping into the delay chain, and combining the plurality of phase-shifted clock in combinational logic to produce an output clock having a frequency that is a multiple of the input clock frequency.

Dependencies are inferred from the claim text.