G06F 7/49952
Sticky bit
Official title: {Sticky bit}
G06F7/49952 (Sticky bit) appears on 73 US grants and 12 published applications in this corpus.
Search patents in G06F- Granted patents
- 73
- Published applications
- 12
- Assignees
- 36
- Inventors
- 118
- Latest grant
- 24 Dec 2019
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 1 | 0 |
| 1989 | 1 | 0 |
| 1990 | 4 | 0 |
| 1991 | 2 | 0 |
| 1992 | 2 | 0 |
| 1993 | 7 | 0 |
| 1994 | 3 | 0 |
| 1995 | 4 | 0 |
| 1996 | 1 | 0 |
| 1997 | 3 | 0 |
| 1998 | 14 | 0 |
| 1999 | 7 | 0 |
| 2000 | 5 | 0 |
| 2001 | 1 | 0 |
| 2002 | 2 | 1 |
| 2003 | 2 | 1 |
| 2004 | 1 | 1 |
| 2005 | 0 | 0 |
| 2006 | 2 | 1 |
| 2007 | 0 | 2 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 2 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 1 | 0 |
| 2014 | 1 | 1 |
| 2015 | 0 | 1 |
| 2016 | 1 | 0 |
| 2017 | 1 | 1 |
| 2018 | 2 | 1 |
| 2019 | 2 | 1 |
| 2020 | 0 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- Multi-input floating-point adder24 Dec 2019US 10,514,891 B1Google Inc.
- Apparatus and method for subtracting significand values of floating-point operands30 Apr 2019US 10,275,218 B1Arm Limited
- Processing denormal numbers in FMA hardware18 Sep 2018US 10,078,512 B2Via Alliance Semiconductor Co., Ltd.
- Partial stochastic rounding that includes sticky and guard bits10 Apr 2018US 9,940,102 B2International Business Machines Corporation
- Arithmetic circuit and arithmetic method25 Apr 2017US 9,632,751 B2Kabushiki Kaisha Toshiba
- Multi-input floating-point adder26 Nov 2020US 2020/0371748 A1Google Inc.
- Apparatus and method for subtracting significand values of floating-point operands25 Apr 2019US 2019/0121615 A1Arm Limited
- Processing denormal numbers in fma hardware5 Apr 2018US 2018/0095749 A1Via Alliance Semiconductor Co., Ltd.
- Partial stochastic rounding that includes sticky and guard bits6 Jul 2017US 2017/0192752 A1International Business Machines Corporation
- Data processing apparatus and method for multiplying floating point operands10 Sep 2015US 2015/0254066 A1Arm Limited
Most cited
By later US patents
- Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals112US 4,589,084 ARCA Corporation · 1986
- Method and apparatus for performing high-precision multiply-add calculations using independent multiply and add instruments102US 5,880,984 AInternational Business Machines Corporation · 1999
- Floating point multiplier with reduced critical paths using delay matching techniques67US 5,790,446 ASun Microsystems, Inc. · 1998
- Multiply-add unit and data processing apparatus using it61US 5,751,621 AHitachi, Ltd. · 1998
- Precision rounding in a floating point arithmetic unit56US 4,758,972 ARaytheon Company · 1988